on a spartan 3e, the DCM speaks to havein a high-resolution phase shifting function, but it goes on and says the DCM has a wide frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase locked? The idea is this, I have a 2MHz signal coming in on a pin, and I want to mimic that signal on an internal std_logic pin with the idea that if the 2MHz signal on the incoming pin is ever lost, the internal std_logic pin continues the original timing as if nothing has happened. Any suggestions?
phase locking a slow (2Mhz) signal.
Started by ●May 27, 2009
Reply by ●May 27, 20092009-05-27
How precise do you need to be? What other clocks do you have in the system? /Mikhail "jleslie48" <jon@jonathanleslie.com> wrote in message news:3848ac2e-9bc7-48f4-9fa0-5ca327a44c8a@r34g2000vbi.googlegroups.com...> on a spartan 3e, the DCM speaks to havein a high-resolution phase > shifting function, but it goes on and says the DCM has a wide > frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > locked? > > The idea is this, I have a 2MHz signal coming in on a pin, and I want > to mimic that signal on an internal std_logic pin with the idea that > if the 2MHz signal on the incoming pin is ever lost, the internal > std_logic pin continues the original timing as if nothing has > happened. > > Any suggestions? >
Reply by ●May 27, 20092009-05-27
On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 <jon@jonathanleslie.com> wrote:>on a spartan 3e, the DCM speaks to havein a high-resolution phase >shifting function, but it goes on and says the DCM has a wide >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase >locked? > >The idea is this, I have a 2MHz signal coming in on a pin, and I want >to mimic that signal on an internal std_logic pin with the idea that >if the 2MHz signal on the incoming pin is ever lost, the internal >std_logic pin continues the original timing as if nothing has >happened. > >Any suggestions?Implement your own NCO. Basically run a high resolution counter with high speed clock and detect at which count the 2MHz signal is toggling (both edges if need be) and generate an internal signal at the same count. Now even if the external signal disappears you have the count (phase) already and you can keep generating the internal signal. You can use this internal signal either as a clock source (ie a divided clock) or as an enable to its downstream logic. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●May 27, 20092009-05-27
On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote:> On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > <j...@jonathanleslie.com> wrote: > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > >shifting function, but it goes on and says the DCM has a wide > >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > >locked? > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > >to mimic that signal on an internal std_logic pin with the idea that > >if the 2MHz signal on the incoming pin is ever lost, the internal > >std_logic pin continues the original timing as if nothing has > >happened. > > >Any suggestions? > > Implement your own NCO. Basically run a high resolution counter with > high speed clock and detect at which count the 2MHz signal is toggling > (both edges if need be) and generate an internal signal at the same > count. Now even if the external signal disappears you have the count > (phase) already and you can keep generating the internal signal. You > can use this internal signal either as a clock source (ie a divided > clock) or as an enable to its downstream logic. > -- > Muzaffer Kal > > DSPIA INC. > ASIC/FPGA Design Services > > http://www.dspia.comas I've been thinking about this today I also thought to forget the DCM and just do it with the regular system clock. The main system clock will be anywhere between 25-100MHZ, and for that matter, the 25MHz can be 4X with the DCM. so now the issue is on the rising edge of the inbound 2MHz clock have the internal 2mhz clock count off 50 ticks of the 100MHz clock to do my best "phase lock"
Reply by ●May 27, 20092009-05-27
On May 27, 4:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote:> On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > <j...@jonathanleslie.com> wrote: > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > >shifting function, but it goes on and says the DCM has a wide > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz signal pha=se> > >locked? > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > > >to mimic that signal on an internal std_logic pin with the idea that > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > >std_logic pin continues the original timing as if nothing has > > >happened. > > > >Any suggestions? > > > Implement your own NCO. Basically run a high resolution counter with > > high speed clock and detect at which count the 2MHz signal is toggling > > (both edges if need be) and generate an internal signal at the same > > count. Now even if the external signal disappears you have the count > > (phase) already and you can keep generating the internal signal. You > > can use this internal signal either as a clock source (ie a divided > > clock) or as an enable to its downstream logic. > > -- > > Muzaffer Kal > > > DSPIA INC. > > ASIC/FPGA Design Services > > >http://www.dspia.com > > as I've been thinking about this today I also thought to forget the > DCM and just do it with the regular system clock. =A0The main system > clock will be anywhere between 25-100MHZ, and for that matter, the > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising edge > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > ticks of the 100MHz clock to do my best "phase lock"Hi Jonathan, I am currently working on the same sort of design. I don't think an NCO is the entire job. What you need is a phase locked loop with a mode of holding the last setting when the input clock is lost. To do this you need an integrator between the phase detector and the NCO which will accumulate and hold a value to maintain the output frequency when the input clock is lost. The trick is this is not a stable circuit and needs other feedback to stabilize it. If you know anything about DSP, this is not a hard problem to analyze. The integrator puts a pole on the unit circle at 1,0 which by itself is not stable. You can add a proportional feedback element to add a zero which can be placed very close to the pole which will stabilize it for frequencies other than near DC. But we don't care about being DC bounded because the feedback loop will compensate for that. Rick
Reply by ●May 28, 20092009-05-28
On May 27, 2:43=A0pm, rickman <gnu...@gmail.com> wrote:> On May 27, 4:10=A0pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > > >shifting function, but it goes on and says the DCM has a wide > > > >frequency range of 5MHz to 300MHz. =A0How can I get my 2MHz signal p=hase> > > >locked? > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I wan=t> > > >to mimic that signal on an internal std_logic pin with the idea that > > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > > >std_logic pin continues the original timing as if nothing has > > > >happened. > > > > >Any suggestions? > > > > Implement your own NCO. Basically run a high resolution counter with > > > high speed clock and detect at which count the 2MHz signal is togglin=g> > > (both edges if need be) and generate an internal signal at the same > > > count. Now even if the external signal disappears you have the count > > > (phase) already and you can keep generating the internal signal. You > > > can use this internal signal either as a clock source (ie a divided > > > clock) or as an enable to its downstream logic. > > > -- > > > Muzaffer Kal > > > > DSPIA INC. > > > ASIC/FPGA Design Services > > > >http://www.dspia.com > > > as I've been thinking about this today I also thought to forget the > > DCM and just do it with the regular system clock. =A0The main system > > clock will be anywhere between 25-100MHZ, and for that matter, the > > 25MHz can be 4X with the DCM. =A0so now the issue is on the rising edge > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > ticks of the 100MHz clock to do my best "phase lock" > > Hi Jonathan, > > I am currently working on the same sort of design. =A0I don't think an > NCO is the entire job. =A0What you need is a phase locked loop with a > mode of holding the last setting when the input clock is lost. =A0To do > this you need an integrator between the phase detector and the NCO > which will accumulate and hold a value to maintain the output > frequency when the input clock is lost. =A0The trick is this is not a > stable circuit and needs other feedback to stabilize it. =A0If you know > anything about DSP, this is not a hard problem to analyze. =A0The > integrator puts a pole on the unit circle at 1,0 which by itself is > not stable. =A0You can add a proportional feedback element to add a zero > which can be placed very close to the pole which will stabilize it for > frequencies other than near DC. =A0But we don't care about being DC > bounded because the feedback loop will compensate for that. > > RickHere is an all-digital solution: Assume we have a high clock frequency, e.g. 100 MHz. We use it to clock a DDS accumulator, whose parallel input is an up/ down counter. We also use the 100 MHz to differentiate the rising edge of the incoming 2 MHz frequency. We check whether this short 10 ns pulse occurs during the High or the Low time of the DDS output square wave. If during the Low level, we increment the up/down counter,(speeding up the DDS output) if during the High level, we decrement the counter. When there is no pulse, we leave the counter value stable, since it remembers the missing frequency. I have not checked whether this circuit will always start under all circumstances. Peter Alfke
Reply by ●May 28, 20092009-05-28
Reply by ●May 28, 20092009-05-28
On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote:> On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > > > > On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > > > On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > > > <j...@jonathanleslie.com> wrote: > > > >on a spartan 3e, the DCM speaks to havein a high-resolution phase > > > >shifting function, but it goes on and says the DCM has a wide > > > >frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > > > >locked? > > > > >The idea is this, I have a 2MHz signal coming in on a pin, and I want > > > >to mimic that signal on an internal std_logic pin with the idea that > > > >if the 2MHz signal on the incoming pin is ever lost, the internal > > > >std_logic pin continues the original timing as if nothing has > > > >happened. > > > > >Any suggestions? > > > > Implement your own NCO. Basically run a high resolution counter with > > > high speed clock and detect at which count the 2MHz signal is toggling > > > (both edges if need be) and generate an internal signal at the same > > > count. Now even if the external signal disappears you have the count > > > (phase) already and you can keep generating the internal signal. You > > > can use this internal signal either as a clock source (ie a divided > > > clock) or as an enable to its downstream logic. > > > -- > > > Muzaffer Kal > > > > DSPIA INC. > > > ASIC/FPGA Design Services > > > >http://www.dspia.com > > > as I've been thinking about this today I also thought to forget the > > DCM and just do it with the regular system clock. The main system > > clock will be anywhere between 25-100MHZ, and for that matter, the > > 25MHz can be 4X with the DCM. so now the issue is on the rising edge > > of the inbound 2MHz clock have the internal 2mhz clock count off 50 > > ticks of the 100MHz clock to do my best "phase lock" > > Hi Jonathan, > > I am currently working on the same sort of design. I don't think an > NCO is the entire job. What you need is a phase locked loop with a > mode of holding the last setting when the input clock is lost. To do > this you need an integrator between the phase detector and the NCO > which will accumulate and hold a value to maintain the output > frequency when the input clock is lost. The trick is this is not a > stable circuit and needs other feedback to stabilize it. If you know > anything about DSP, this is not a hard problem to analyze. The > integrator puts a pole on the unit circle at 1,0 which by itself is > not stable. You can add a proportional feedback element to add a zero > which can be placed very close to the pole which will stabilize it for > frequencies other than near DC. But we don't care about being DC > bounded because the feedback loop will compensate for that. > > RickSorry what does NCO stand for?
Reply by ●May 28, 20092009-05-28
jleslie48 wrote:> On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: >> >> >> >> >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: >> >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 >> >>>><j...@jonathanleslie.com> wrote: >>>> >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phase >>>>>shifting function, but it goes on and says the DCM has a wide >>>>>frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase >>>>>locked? >> >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I want >>>>>to mimic that signal on an internal std_logic pin with the idea that >>>>>if the 2MHz signal on the incoming pin is ever lost, the internal >>>>>std_logic pin continues the original timing as if nothing has >>>>>happened. >> >>>>>Any suggestions? >> >>>>Implement your own NCO. Basically run a high resolution counter with >>>>high speed clock and detect at which count the 2MHz signal is toggling >>>>(both edges if need be) and generate an internal signal at the same >>>>count. Now even if the external signal disappears you have the count >>>>(phase) already and you can keep generating the internal signal. You >>>>can use this internal signal either as a clock source (ie a divided >>>>clock) or as an enable to its downstream logic. >>>>-- >>>>Muzaffer Kal >> >>>>DSPIA INC. >>>>ASIC/FPGA Design Services >> >>>>http://www.dspia.com >> >>>as I've been thinking about this today I also thought to forget the >>>DCM and just do it with the regular system clock. The main system >>>clock will be anywhere between 25-100MHZ, and for that matter, the >>>25MHz can be 4X with the DCM. so now the issue is on the rising edge >>>of the inbound 2MHz clock have the internal 2mhz clock count off 50 >>>ticks of the 100MHz clock to do my best "phase lock" >> >>Hi Jonathan, >> >>I am currently working on the same sort of design. I don't think an >>NCO is the entire job. What you need is a phase locked loop with a >>mode of holding the last setting when the input clock is lost. To do >>this you need an integrator between the phase detector and the NCO >>which will accumulate and hold a value to maintain the output >>frequency when the input clock is lost. The trick is this is not a >>stable circuit and needs other feedback to stabilize it. If you know >>anything about DSP, this is not a hard problem to analyze. The >>integrator puts a pole on the unit circle at 1,0 which by itself is >>not stable. You can add a proportional feedback element to add a zero >>which can be placed very close to the pole which will stabilize it for >>frequencies other than near DC. But we don't care about being DC >>bounded because the feedback loop will compensate for that. >> >>Rick > > > Sorry what does NCO stand for? >It is also called a DDS for Direct Digital Synthesizer. Analog devices makes a family of them. And they are very nice units. Basically they are a phase accumulator. The frequency output is equal to the clock frequency times the phase count divided by the counter full scale. The big advantage is that the step size is constant and is the clock frequency divided by the counter size. Thus a 24bit counter and a 16MHz clock gives a step size of 1Hz. Compare this with a frequency divider where you get an output of f, f/2, f/3 etc. The downside is that there is some jitter (up to one clock period) and that makes it difficult to use in some low noise applications. The commercial devices have a sin ROM and a D/A to give a nice sine wave output. They are useful in FPGAs where you can track moving input clocks. Rick's comments above are quite correct in that you can make a PLL in the fpga digitally.
Reply by ●May 28, 20092009-05-28
On May 28, 3:32 pm, doug <x...@xx.com> wrote:> jleslie48 wrote: > > On May 27, 5:43 pm, rickman <gnu...@gmail.com> wrote: > > >>On May 27, 4:10 pm, jleslie48 <j...@jonathanleslie.com> wrote: > > >>>On May 27, 1:33 pm, Muzaffer Kal <k...@dspia.com> wrote: > > >>>>On Wed, 27 May 2009 08:17:05 -0700 (PDT), jleslie48 > > >>>><j...@jonathanleslie.com> wrote: > > >>>>>on a spartan 3e, the DCM speaks to havein a high-resolution phase > >>>>>shifting function, but it goes on and says the DCM has a wide > >>>>>frequency range of 5MHz to 300MHz. How can I get my 2MHz signal phase > >>>>>locked? > > >>>>>The idea is this, I have a 2MHz signal coming in on a pin, and I want > >>>>>to mimic that signal on an internal std_logic pin with the idea that > >>>>>if the 2MHz signal on the incoming pin is ever lost, the internal > >>>>>std_logic pin continues the original timing as if nothing has > >>>>>happened. > > >>>>>Any suggestions? > > >>>>Implement your own NCO. Basically run a high resolution counter with > >>>>high speed clock and detect at which count the 2MHz signal is toggling > >>>>(both edges if need be) and generate an internal signal at the same > >>>>count. Now even if the external signal disappears you have the count > >>>>(phase) already and you can keep generating the internal signal. You > >>>>can use this internal signal either as a clock source (ie a divided > >>>>clock) or as an enable to its downstream logic. > >>>>-- > >>>>Muzaffer Kal > > >>>>DSPIA INC. > >>>>ASIC/FPGA Design Services > > >>>>http://www.dspia.com > > >>>as I've been thinking about this today I also thought to forget the > >>>DCM and just do it with the regular system clock. The main system > >>>clock will be anywhere between 25-100MHZ, and for that matter, the > >>>25MHz can be 4X with the DCM. so now the issue is on the rising edge > >>>of the inbound 2MHz clock have the internal 2mhz clock count off 50 > >>>ticks of the 100MHz clock to do my best "phase lock" > > >>Hi Jonathan, > > >>I am currently working on the same sort of design. I don't think an > >>NCO is the entire job. What you need is a phase locked loop with a > >>mode of holding the last setting when the input clock is lost. To do > >>this you need an integrator between the phase detector and the NCO > >>which will accumulate and hold a value to maintain the output > >>frequency when the input clock is lost. The trick is this is not a > >>stable circuit and needs other feedback to stabilize it. If you know > >>anything about DSP, this is not a hard problem to analyze. The > >>integrator puts a pole on the unit circle at 1,0 which by itself is > >>not stable. You can add a proportional feedback element to add a zero > >>which can be placed very close to the pole which will stabilize it for > >>frequencies other than near DC. But we don't care about being DC > >>bounded because the feedback loop will compensate for that. > > >>Rick > > > Sorry what does NCO stand for? > > It is also called a DDS for Direct Digital Synthesizer. Analog devices > makes a family of them. And they are very nice units. Basically they > are a phase accumulator. The frequency output is equal to the clock > frequency times the phase count divided by the counter full scale. > The big advantage is that the step size is constant and is the > clock frequency divided by the counter size. Thus a 24bit counter > and a 16MHz clock gives a step size of 1Hz. Compare this with a > frequency divider where you get an output of f, f/2, f/3 etc. > The downside is that there is some jitter (up to one clock period) > and that makes it difficult to use in some low noise applications. > The commercial devices have a sin ROM and a D/A to give a nice > sine wave output. They are useful in FPGAs where you can track > moving input clocks. Rick's comments above are quite correct in > that you can make a PLL in the fpga digitally. > >Numerically Controlled Oscillator > >/MikhailAhh, thanks again all.
