Hi everyone, I cannot simulate a simple AND Gate the original project: I have downloaded the AND gate VHDL to a CPLD and it works file without adding extra bits to simulate. You create the ucf file and download to the CPLD and then real time I've tested the out put and it works fine I am getting to the AND gate project becuase I am having problem simulating bigger VHDL code. trying to understand the basic. When I simulate in ISim from 11.1 suite, I went step by step and I figured out the simulation only run through the code outputC <= inputA and inputB; only once. So I added a SEQ and simulater again and this time it does do back to the VHDL file and run outputC <= inputA and inputB; every time the clk rising the problem I have now is I cannot simulate a simple AND Gate in Isim look at the tb file I have create when inputA is like the clock, inputB is high always, but outputC is dead Could you please help??? Thanks This is the original project ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MyANDGate is Port (inputA : in STD_LOGIC; inputB : in STD_LOGIC; outputC : out STD_LOGIC); end MyANDGate; architecture Behavioral of MyANDGate is begin outputC <= inputA and inputB; end Behavioral; ______________________________________________________ Adding bit for simulation VHDL file ---------------------------------------------------------------------------------- library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; ---- Uncomment the following library declaration if instantiating ---- any Xilinx primitives in this code. --library UNISIM; --use UNISIM.VComponents.all; entity MyANDGate is Port ( clk : in STD_LOGIC; -- simulation purpose only inputA : in STD_LOGIC; inputB : in STD_LOGIC; outputC : out STD_LOGIC); end MyANDGate; architecture Behavioral of MyANDGate is begin SEQ: process(clk) begin if (clk'event and clk = '1') then outputC <= inputA and inputB; end if; end process SEQ; end Behavioral; _______________________________________________________________ the tb file LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_unsigned.all; USE ieee.numeric_std.ALL; ENTITY MyANDGate_tb IS END MyANDGate_tb; ARCHITECTURE behavior OF MyANDGate_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT MyANDGate PORT( clk : in std_logic; inputA : IN std_logic; inputB : IN std_logic; outputC : OUT std_logic ); END COMPONENT; --Inputs signal clk : std_logic := '0'; signal inputA : std_logic := '0'; signal inputB : std_logic := '1'; --Outputs signal outputC : std_logic; constant clk_period : time := 0.5425347us; BEGIN -- Instantiate the Unit Under Test (UUT) uut: MyANDGate PORT MAP ( clk => clk, inputA => inputA, inputB => inputB, outputC => outputC ); -- No clocks detected in port list. Replace <clock> below with -- appropriate port name clk_process :process begin clk <= '0'; inputA <= '0'; wait for clk_period/2; clk <= '1'; inputA <= '1'; wait for clk_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 100ms. wait for 100ms; wait for clk_period*10; -- insert stimulus here wait; end process; END;
Urgent help with a Simple AND simulation
Started by ●May 29, 2009
Reply by ●May 29, 20092009-05-29
Peter wrote:> Hi everyone, > I cannot simulate a simple AND Gate > > the original project: > I have downloaded the AND gate VHDL to a CPLD and it works file > without adding extra bits to simulate. > You create the ucf file and download to the CPLD and then real time > I've tested the out put and it works fine > > I am getting to the AND gate project becuase I am having problem > simulating bigger VHDL code. trying to understand the basic. > > When I simulate in ISim from 11.1 suite, I went step by step and I > figured out the simulation only run through the code outputC <= > inputA and inputB; only once. > > So I added a SEQ and simulater again and this time it does do back to > the VHDL file and run outputC <= inputA and inputB; every time the > clk rising > > the problem I have now is I cannot simulate a simple AND Gate in Isim > look at the tb file I have create when inputA is like the clock, > inputB is high always, but outputC is dead > > Could you please help??? Thanks >Look at the relationship of the CLK, inputA, inputB in the simulator.
Reply by ●May 30, 20092009-05-30
This is fix now the problem was the "if clock" was evaluating the signal only when the clock/inputA is in high, after removing that condition the output works as it should. Thanks
Reply by ●May 30, 20092009-05-30