Re: Xilinx GbE performance

On Jun 3, 5:33=A0am, "john.orla...@gmail.com" <john.orla...@gmail.com>
wrote:
> <snip>
>
>
>
>
>
> > > > > hum.. my current task is to optimize a XPS_TEMAC based system
> > > > > (with 1 single DDR2 chip as main memory!)
> > > > > to reach about 580MBps
>
> > > > > :(
>
> > > > > I have never said that to be possible, but i need money :(
> > > > > and if the goal cant be reached there will be none...
>
> > > > > over 100MBps is sure possible (with XPS_TEMAC too)
> > > > > =A0but 580MBps is beyong doable i think for sure
>
> > > > > Antti
>
> > > > Just a simple calculation:
> > > > 125000000 / 1024 / 1024 =3D 119.2MBps
> > > > It is without protocol overhead, FCS, IFGs. How do you want to exce=
ed
> > > > limit of Gigabit Ethernet?
>
> > > > Jan
>
> > > Or did I get you wrong and you talk about Mbits per second? I was
> > > talking about Mbytes per sec.
> > > If it is so, your goal should be reachable using xps_ll_temac instead=
 of
> > > xps_temac.
> > > Jan
>
> > oh, i am talking wrong today
> > yes Mbit/sec or Mbps
> > and sure XPS_LL_TEMAC with ALL hardware options tuned to maximum
> > and we do not copy buffers, and do not calc UDP checksum with PPC
>
> > but, even TRECKs marketing booklet promised only 355 Mbps for MTU1500
> > abd i need 580Mbps
>
> > Antti
>
> Antti,
> The USRP2 (http://en.wikipedia.org/wiki/
> Universal_Software_Radio_Peripheral) is a software-defined radio that
> uses a Spartan III + gigE PHY chip to reach 800 Mbits/sec sustained.
> I believe the MAC in their FPGA has a few limitations (only supports
> 1000 Base-T) but was originally based on the opencores tri-mode MAC
> (though significant modifications were needed to make it reliable,
> IIRC). =A0The other caveat here is that the USRP2 guys push raw ethernet
> frames into a PC...i.e., they don't use TCP or UDP. =A0I believe their
> analysis showed that they needed a custom network layer to support the
> sustained high data rates.
>
> So I wouldn't give up hope on making something work here at 580 Mbits/
> sec. =A0All of the USRP2 code (software + HDL) is open-sourced, and
> should be available through their subversion repositories.
>
> Good Luck,
> John


I'm using UDP and getting sustainable 600-700Mbits/sec. In fact this
number is limited by the PC side: either a network card or a stack.

- outputlogic

Jan Pech avait soumis l'id�e :
> On Tue, 2009-06-02 at 09:53 -0700, Antti wrote:
>> Hi
>> 
>> does anybody have real and realistic performance figures for Xilinx
>> GbE solution with XPS_TEMAC/MPMC ?
>> 
>> we need to get 60% of GbE wirespeed, UDP transmit only but it seems
>> like real hard target to reach :(
>> 
>> MPMC has memory latency of 23 cycles (added to EACH memory access
>> cycle) so the ethernet
>> SDMA takes a lot of bandwith already, there is another DMA writing
>> data at same speed, and the
>> PPC itself uses the same memory too
>> 
>> Antti
>
> With custom Ethernet core + MPMC we get data rates slightly above
> 100MBps, depending on MTU. The single memory is shared by MicroBlaze/PPC
> for code and data access, at least one streaming data source (custom PIM
> for NPI) and the custom Ethernet IP (MAC + some packet composers,
> decoders, etc.) again connected to NPI.
> We rejected to use XPS_TEMAC because its low performance. The problem is
> I lost my benchmark results. Sorry.
>
> Jan

Hello,

FYI, we've developed a while ago a solution we name GEDEK that 
implements 100% GbE performance (we guarantee the simultaneous 
generation and reception of back-to-back Gigabit Ethernet Frames 
without delay nor loss, and our hardware stack has UDP, some ICMP & 
ARP, without requiring a processor (hardware stack indeed). Available & 
tested on Xilinx & Altera, 100M, 1GbE, or dual-speed. We provide botrh 
ends (FPGA block and PC Win/Linux API in source code). We have options 
for Remote Flash Programming, Virtual UARTs, WOL etc.
Documentation and demos for both vendors are available on demand at 
info at alse-fr not calm.

Bert