digital RGB Video to Analog VGA triple DAC question

I am looking at doing an FPGA video processor board design for with an
analog VGA style component output.

I have looked at quite a few video DACs from TI, NXP, Analog
Devices, that will do this. Most of the parts I have seen can do
component VGA style and composite NTSC style outputs.

Now, most VGA style interfaces require 3 analog video pins, as well as
two digital sync pins (VSYNC & HSYNC).
(see: http://en.wikipedia.org/wiki/VGA_connector )
The video DAC parts typically do not generate these digital outputs. I
am left with the task of driving them from the FPGA.
There are two things that concern me. One is delay. How much delay is
induced on the pixels by the video DAC?
Do I even need to worry about delaying the sync signals out of the
FPGA in order to match the delay inherent in
going from digital to analog in the video DAC? In other words, do I
need to worry about delaying the sync signal outputs from the FPGA
to match the delay inherent in the digital to analog converter IC
in order to make the analog pixel signals temporally aligned with the
digital sync signals? Perhaps the conversion delay is so slight that
it is only of concern at higher resolutions?

The second concern has to do with signal voltage levels/current
strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
with whatever my VGA receiver is expecting to see at its inputs? Do I
need some kind of level shifter or buffer to make this work?


Thanks for your help.

wallge <wallge@gmail.com> wrote:

>I am looking at doing an FPGA video processor board design for with an
>analog VGA style component output.
>
>I have looked at quite a few video DACs from TI, NXP, Analog
>Devices, that will do this. Most of the parts I have seen can do
>component VGA style and composite NTSC style outputs.
>
>Now, most VGA style interfaces require 3 analog video pins, as well as
>two digital sync pins (VSYNC & HSYNC).
>(see: http://en.wikipedia.org/wiki/VGA_connector )
>The video DAC parts typically do not generate these digital outputs. I
>am left with the task of driving them from the FPGA.
>There are two things that concern me. One is delay. How much delay is
>induced on the pixels by the video DAC?
>Do I even need to worry about delaying the sync signals out of the
>FPGA in order to match the delay inherent in

No. The sync signals are pretty low frequency anyway and transported
over non balanced lines. I suspect TFT monitors use the RGB signals to
lock the image on.

>The second concern has to do with signal voltage levels/current
>strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
>with whatever my VGA receiver is expecting to see at its inputs? Do I
>need some kind of level shifter or buffer to make this work?

Some very old CRT monitors may not like 3.3V signals. I had some
problems with that 10 years ago. But most monitors with TTL compliant
inputs will work fine.

-- 
Failure does not prove something is impossible, failure simply
indicates you are not using the right tools...
                     "If it doesn't fit, use a bigger hammer!"
--------------------------------------------------------------

wallge <wallge@gmail.com> wrote:
< I am looking at doing an FPGA video processor board design for with an
< analog VGA style component output.
(snip)

< Now, most VGA style interfaces require 3 analog video pins, 
< as well as two digital sync pins (VSYNC & HSYNC).

Not knowing the exact answer, I believe that many can find the
sync signal on the green input if VSYNC and HSYNC aren't provided.

(snip on timing)
 
< The second concern has to do with signal voltage levels/current
< strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
< with whatever my VGA receiver is expecting to see at its inputs? Do I
< need some kind of level shifter or buffer to make this work?

I believe the usual case is a series resistor such that into
a 75 ohm load the appropriate voltage is supplied.  Well,
that may be more for the video signal, but also in many cases
for the sync signal.   Find the expected voltage and input
impedance for your monitor.

-- glen

On Fri, 5 Jun 2009 12:29:11 -0700 (PDT)
wallge <wallge@gmail.com> wrote:

> I am looking at doing an FPGA video processor board design for with an
> analog VGA style component output.
> 
> I have looked at quite a few video DACs from TI, NXP, Analog
> Devices, that will do this. Most of the parts I have seen can do
> component VGA style and composite NTSC style outputs.
> 
> Now, most VGA style interfaces require 3 analog video pins, as well as
> two digital sync pins (VSYNC & HSYNC).
> (see: http://en.wikipedia.org/wiki/VGA_connector )
> The video DAC parts typically do not generate these digital outputs. I
> am left with the task of driving them from the FPGA.
> There are two things that concern me. One is delay. How much delay is
> induced on the pixels by the video DAC?
> Do I even need to worry about delaying the sync signals out of the
> FPGA in order to match the delay inherent in
> going from digital to analog in the video DAC? In other words, do I
> need to worry about delaying the sync signal outputs from the FPGA
> to match the delay inherent in the digital to analog converter IC
> in order to make the analog pixel signals temporally aligned with the
> digital sync signals? Perhaps the conversion delay is so slight that
> it is only of concern at higher resolutions?
> 
> The second concern has to do with signal voltage levels/current
> strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
> with whatever my VGA receiver is expecting to see at its inputs? Do I
> need some kind of level shifter or buffer to make this work?
> 
> 
> Thanks for your help.

Don't know much about the specifics of your video signal, but I always
try to have the cheapest possible part coming out to a connector.
Regardless of whether you need any voltage translation or not on those
digital signals, a $0.13 SC-70 dual buffer chip will a) allow you to put
the high Icc transients needed to drive the capacitive cable
somewhere outside of your FPGA and b) hopefully sacrifice itself to
save your FPGA in the event of a 30kV ESD zap.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Jun 5, 5:35=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> wallge <wal...@gmail.com> wrote:
>
> < I am looking at doing an FPGA video processor board design for with an
> < analog VGA style component output.
> (snip)
>
> < Now, most VGA style interfaces require 3 analog video pins,
> < as well as two digital sync pins (VSYNC & HSYNC).
>
> Not knowing the exact answer, I believe that many can find the
> sync signal on the green input if VSYNC and HSYNC aren't provided.
>
> (snip on timing)
>
> < The second concern has to do with signal voltage levels/current
> < strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
> < with whatever my VGA receiver is expecting to see at its inputs? Do I
> < need some kind of level shifter or buffer to make this work?
>
> I believe the usual case is a series resistor such that into
> a 75 ohm load the appropriate voltage is supplied. =A0Well,
> that may be more for the video signal, but also in many cases
> for the sync signal. =A0 Find the expected voltage and input
> impedance for your monitor.
>
> -- glen

75 Ohm loading is on the video signals only.  The TTL signals
should be source series terminated presuming a high impedance
at the monitor.  Analog CRT's had a wide range of timing
between sync and video, and usually had some sort of knob
or menu control to adjust the picture.  Newer LCD monitors
run through a sequence of steps to automatically adjust
the picture to the syncs they receive.

Most PC video does not use sync-on-green, but many of the
DAC's provide the capability af adding the integrated
sync, which is then usually the XOR of horizontal and
vertical sync.  Some DAC's also provide for HDTV style
three-level syncs.  If your only requirement is to drive
a standard PC monitor you don't need sync on green.

More important to LCD monitors is to get the number of
pixel clocks per horizontal line period correct.  There
is a good site for calculating the timing to meet the
various VESA standards at:

http://www.hut.fi/Misc/Electronics/faq/vga2rgb/calc.html

Regards,
Gabor

On Fri, 5 Jun 2009 15:03:37 -0700 (PDT), gabor <gabor@alacron.com> wrote:

>On Jun 5, 5:35&#4294967295;pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>> wallge <wal...@gmail.com> wrote:
>>
>> < I am looking at doing an FPGA video processor board design for with an
>> < analog VGA style component output.
>> (snip)

Take a look at the Chrontel CH7301A - it does analogue VGA and DVI output, and has a DDR input to
save on pins. 

On Jun 6, 2:11=A0am, Mike Harrison <m...@whitewing.co.uk> wrote:
> On Fri, 5 Jun 2009 15:03:37 -0700 (PDT), gabor <ga...@alacron.com> wrote:
> >On Jun 5, 5:35=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> >> wallge <wal...@gmail.com> wrote:
>
> >> < I am looking at doing an FPGA video processor board design for with =
an
> >> < analog VGA style component output.
> >> (snip)
>
> Take a look at the Chrontel CH7301A - it does analogue VGA and DVI output=
, and has a DDR input to
> save on pins.

I have actually been considering the chrontel parts... the DDR input
is one thing that concerns me. For some applications I will have to
run my video at 1280x1024@60Hz (SXGA). This VESA clock speed for this
is 108MHz. My current system design will have the FPGA on a main
processor board and my VGA converter chip on a separate breakout IO
board. If I have to DDR-ize my SXGA outputs, we are now talking about
signals transitioning at 216MHz, which makes me worry about signal
integrity and timing issues. I am using a Cyclone III and am not sure
if I can meet this timing. I am also worried about these single ended
signals traversing the board to board connector between the FPGA board
and the breakout IO board... Anyone have an opinion on this?
Also, do these DDR signals need to by at 2.5V standard, or will 3.3V
TTL/CMOS work just fine?

On Sat, 6 Jun 2009 02:56:35 -0700 (PDT), wallge <wallge@gmail.com> wrote:

>On Jun 6, 2:11&#4294967295;am, Mike Harrison <m...@whitewing.co.uk> wrote:
>> On Fri, 5 Jun 2009 15:03:37 -0700 (PDT), gabor <ga...@alacron.com> wrote:
>> >On Jun 5, 5:35&#4294967295;pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
>> >> wallge <wal...@gmail.com> wrote:
>>
>> >> < I am looking at doing an FPGA video processor board design for with an
>> >> < analog VGA style component output.
>> >> (snip)
>>
>> Take a look at the Chrontel CH7301A - it does analogue VGA and DVI output, and has a DDR input to
>> save on pins.
>
>I have actually been considering the chrontel parts... the DDR input
>is one thing that concerns me. For some applications I will have to
>run my video at 1280x1024@60Hz (SXGA). This VESA clock speed for this
>is 108MHz. My current system design will have the FPGA on a main
>processor board and my VGA converter chip on a separate breakout IO
>board. If I have to DDR-ize my SXGA outputs, we are now talking about
>signals transitioning at 216MHz, which makes me worry about signal
>integrity and timing issues. I am using a Cyclone III and am not sure
>if I can meet this timing. I am also worried about these single ended
>signals traversing the board to board connector between the FPGA board
>and the breakout IO board... Anyone have an opinion on this?
>Also, do these DDR signals need to by at 2.5V standard, or will 3.3V
>TTL/CMOS work just fine?

The CH7301 has a Vref input to set the threshold of the digital inputs, and the IO power supply
range is specced as 1.1 to 3.3v, so 2.5v should be fine

On Jun 5, 9:29=A0pm, wallge <wal...@gmail.com> wrote:
> Do I even need to worry about delaying the sync signals out of the
> FPGA in order to match the delay inherent in
> going from digital to analog in the video DAC? In other words, do I
> need to worry about delaying the sync signal outputs from the FPGA
> to match the delay inherent in the digital to analog converter IC
> in order to make the analog pixel signals temporally aligned with the
> digital sync signals? Perhaps the conversion delay is so slight that
> it is only of concern at higher resolutions?


I think it depend on how big is the delay! Usually vga monitor are a
little bit tolerant...
Before and after the h/v sync time there are a "back-pork" time and a
"front-pork" time and if you use more time for the front-pork and less
for the back-pork then the display usually simply show the image a
little bit
to the left or to the right (up/down for vertical sync) but you should
be able
to tune the monitor with his controls (some monitor have auto-tuning
features...).


>
> The second concern has to do with signal voltage levels/current
> strength. Are the 3.3V LVTTL/LVCMOS outputs from my FPGA compatible
> with whatever my VGA receiver is expecting to see at its inputs? Do I
> need some kind of level shifter or buffer to make this work?


The r/g/b signals are in the range 0 - 0.7 V. if you use only a bit
per color
component (3 bit total) then you can drive it directly from the fpga
with
a 270 ohm series resistor ( + 75 of the vga cable) you obtain 0.7 V
when
the fpga pin is at 3.3 v)
For the v/h sync it suffice a 82.5 ohm.

Please take a look here
   http://www.opencores.org/?do=3Dproject&who=3Dyavga
There is a very simple schematic using 1 bit per color component and
if you get the vhdl sources, in the vga_ctrl.vhd file you can find
some information about the vga timings embedded in the vhdl as
comment.

For better resuld (8 bit per color component) you must use a DAC for r/
g/b
and a 82.5 ohm series resistor for h/v sync signals.

Maybe you can obtain something functional with a
resistor ladder too (http://en.wikipedia.org/wiki/Resistor_ladder)
but I didn't try (I don't know how a resistor ladder behave with
a signal at high frequency as the pixel clock for 1280x1024).

Regards
Sandro

> I am looking at doing an FPGA video processor board design for with an
> analog VGA style component output.
>
Hi,

FWIW, we have recently implemented a Full HD 1080p demo on the very 
affordable Altera NEEK Kit ! The output image quality is just perfect. 
But amazingly (well, not so much so), we had to try two VGA cables to 
get the image perfect. Pixel freq is quite high for Full HD...
1280x1024-60Hz is easier.
The BOM for the system required by this demo is very low cost (a small 
Cyclone III, Flash memory, cheap DDR and video DAC). The demo uses also 
the embedded video in -> bt656 codec (PAL or NTSC autoswitch) and we 
resize the video dynamically while displaying a full HD resolution 
background with dynamic OSD and alpha blending.
The schematics of the Kit as well as all the documentation are 
available on the Altera website. This includes the video section indeed 
so you can check. 
http://www.altera.com/products/devkits/altera/kit-cyc3-embedded.html
The multimedia extension section can be bought separately (from the FGA 
board) at Terasic.com.

There is also a VGA DAC snap on board that we've used in the past named 
Lancelot (used to be at www.fpga.nl ?). I think it used a TI DAC, not 
sure how high it could go, we haven't tried Full HD on this one.

Hope this helps,
Bert.