FDRSE Spartan 3A - Active high/low set/reset

Hi,

I have to instantiate (not inference) two FDRSE elements in my VHDL-
Code.

FDRSE1 should have active-high set/reset.
FDRSE2 should have active-low  set/reset.

This is the instantiation code from the Libraries Guide:

FDRSE_inst : FDRSE
generic map (INIT => '0') -- Initial value of register ('0' or '1')
port map (
                  Q    => Q,      -- Data output
                  C    => C,      -- Clock input
                  CE => CE,    -- Clock enable input
                  D   => D,      -- Data input
                  R   => R,      -- Synchronous reset input
                  S   => S       -- Synchronous set input
);

In this instantiation code, there is no possibility to configure the
set/reset polarity.

My two questions are:

1. How to instantiate a FDRSE with active-high set/reset
2. How to instantiate a FDRSE with active-low  set/reset

Thanks in advance,
Mark Lenz

On Fri, 19 Jun 2009 09:50:27 -0700 (PDT)
lenz19@gmx.de wrote:

> Hi,
> 
> I have to instantiate (not inference) two FDRSE elements in my VHDL-
> Code.
> 
> FDRSE1 should have active-high set/reset.
> FDRSE2 should have active-low  set/reset.
> 
> This is the instantiation code from the Libraries Guide:
> 
> FDRSE_inst : FDRSE
> generic map (INIT => '0') -- Initial value of register ('0' or '1')
> port map (
>                   Q    => Q,      -- Data output
>                   C    => C,      -- Clock input
>                   CE => CE,    -- Clock enable input
>                   D   => D,      -- Data input
>                   R   => R,      -- Synchronous reset input
>                   S   => S       -- Synchronous set input
> );
> 
> In this instantiation code, there is no possibility to configure the
> set/reset polarity.
> 
> My two questions are:
> 
> 1. How to instantiate a FDRSE with active-high set/reset
> 2. How to instantiate a FDRSE with active-low  set/reset
> 
> Thanks in advance,
> Mark Lenz
> 

1. You just did.
2. R => not R, S => not S

Out of curiosity, why would you need to be directly instantiating
flops?  I've found very few situations where that's actually the right
answer (ripple counters, etc).

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Jun 19, 10:49=A0am, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 19 Jun 2009 09:50:27 -0700 (PDT)
>
>
>
> len...@gmx.de wrote:
> > Hi,
>
> > I have to instantiate (not inference) two FDRSE elements in my VHDL-
> > Code.
>
> > FDRSE1 should have active-high set/reset.
> > FDRSE2 should have active-low =A0set/reset.
>
> > This is the instantiation code from the Libraries Guide:
>
> > FDRSE_inst : FDRSE
> > generic map (INIT =3D> '0') -- Initial value of register ('0' or '1')
> > port map (
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Q =A0 =A0=3D> Q, =A0 =A0 =A0-- Data=
 output
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 C =A0 =A0=3D> C, =A0 =A0 =A0-- Cloc=
k input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CE =3D> CE, =A0 =A0-- Clock enable =
input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 D =A0 =3D> D, =A0 =A0 =A0-- Data in=
put
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 R =A0 =3D> R, =A0 =A0 =A0-- Synchro=
nous reset input
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 S =A0 =3D> S =A0 =A0 =A0 -- Synchro=
nous set input
> > );
>
> > In this instantiation code, there is no possibility to configure the
> > set/reset polarity.
>
> > My two questions are:
>
> > 1. How to instantiate a FDRSE with active-high set/reset
> > 2. How to instantiate a FDRSE with active-low =A0set/reset
>
> > Thanks in advance,
> > Mark Lenz
>
> 1. You just did.
> 2. R =3D> not R, S =3D> not S
>
> Out of curiosity, why would you need to be directly instantiating
> flops? =A0I've found very few situations where that's actually the right
> answer (ripple counters, etc).
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

I believe XST will not directly infer DDR output flops.  At least it
didn't used to be
able to do this.  I've always had to instantiate DDR output flops.

John Providenza

Rob, John thanks for reply.


>> 2. R => not R, S => not S


That's the point.
Your suggestion would infer an inverter realized in a LUT.
I don't want to infer extra inverter logic in the CLB. I want the
inverter for free.

In the Storage Elements Section of the User Guide for Spartan it is
statet that
"All signals have programmable polarity; the default active-High
function is described."

So, I am looking for a way to configure the polarity of the set/reset
signals of a FDRSE.


>> Out of curiosity, why would you need to be directly instantiating flops?


I want to use the three inputs (set, reset and data) of the FDRSE at
the same time
without infering extra LUT-Logic.

Something like this:

Connect signal a to set-input, signal b to reset-input and signal c to
data-input.


Thanks for your contribution.

On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
lenz19@gmx.de wrote:

> Rob, John thanks for reply.
> 
> 
> >> 2. R => not R, S => not S
> 
> 
> That's the point.
> Your suggestion would infer an inverter realized in a LUT.
> I don't want to infer extra inverter logic in the CLB. I want the
> inverter for free.
> 

That's why there's a synthesis tool that's able to perform
optimization.  Last I checked, if you go back in to the FPGA Editor
and look in on what you've got, you'll find that XST will very
happily have collapsed those inverters into the free ones built into
the slice.

You seem to be of the opinion that it's necessary for you to outsmart
the synthesis tools.  As I said earlier, it's really rarely the case.
If you code:

process(clk, r, s)
begin
  if (r = '1') then
    q <= '0';
  elsif (s = '1') then
    q <= '1';
  elseif rising_edge(clk) then
    q <= d;
  end if;
end process;

You'll find that the synthesis tool still gives you exactly what you
wanted, without you having to slog through unnecessary direct
instatiation.  The people telling you that it doesn't work haven't updated their opinions since the mid 1990s.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On 20 Jun., 02:19, Rob Gaddi <rga...@technologyhighland.com> wrote:
> On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
>
> len...@gmx.de wrote:
> > Rob, John thanks for reply.
>
> > >> 2. R =3D> not R, S =3D> not S
>
> > That's the point.
> > Your suggestion would infer an inverter realized in a LUT.
> > I don't want to infer extra inverter logic in the CLB. I want the
> > inverter for free.
>
> That's why there's a synthesis tool that's able to perform
> optimization. =A0Last I checked, if you go back in to the FPGA Editor
> and look in on what you've got, you'll find that XST will very
> happily have collapsed those inverters into the free ones built into
> the slice.
>
> You seem to be of the opinion that it's necessary for you to outsmart
> the synthesis tools. =A0As I said earlier, it's really rarely the case.
> If you code:
>
> process(clk, r, s)
> begin
> =A0 if (r =3D '1') then
> =A0 =A0 q <=3D '0';
> =A0 elsif (s =3D '1') then
> =A0 =A0 q <=3D '1';
> =A0 elseif rising_edge(clk) then
> =A0 =A0 q <=3D d;
> =A0 end if;
> end process;
>
> You'll find that the synthesis tool still gives you exactly what you
> wanted, without you having to slog through unnecessary direct
> instatiation. =A0The people telling you that it doesn't work haven't upda=
ted their opinions since the mid 1990s.
>
> --
> Rob Gaddi, Highland Technology
> Email address is currently out of order

I will try this and give you a feedback whether it worked or not.

Thank you for sharing your knowledge.

On 2009-06-19, john <jprovidenza@yahoo.com> wrote:
> I believe XST will not directly infer DDR output flops.  At least it
> didn't used to be
> able to do this.  I've always had to instantiate DDR output flops.

Another reason to manually instantiate a flip-flop is when the synthesis tool
is doing something suboptimal. For example, I've noticed that XST relatively
often places my critical path on the SR input of flip-flops even though that
path is quite a bit slower than the D input. In those cases I usually
instantiate the flip-flop manually to control what is going on.

(It is possible that a synthesis keep option would also help here though instead
of manually instantiating the flip-flop.)

/Andreas

Rob Gaddi wrote:
> On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
> lenz19@gmx.de wrote:
> 
>> Rob, John thanks for reply.
>>
>>
>>>> 2. R => not R, S => not S
>>
>> That's the point.
>> Your suggestion would infer an inverter realized in a LUT.
>> I don't want to infer extra inverter logic in the CLB. I want the
>> inverter for free.
>>
> 
> That's why there's a synthesis tool that's able to perform
> optimization.  Last I checked, if you go back in to the FPGA Editor
> and look in on what you've got, you'll find that XST will very
> happily have collapsed those inverters into the free ones built into
> the slice.
> 
> You seem to be of the opinion that it's necessary for you to outsmart
> the synthesis tools.  As I said earlier, it's really rarely the case.
> If you code:
> 
> process(clk, r, s)
> begin
>   if (r = '1') then
>     q <= '0';
>   elsif (s = '1') then
>     q <= '1';
>   elseif rising_edge(clk) then
>     q <= d;
>   end if;
> end process;
> 
> You'll find that the synthesis tool still gives you exactly what you
> wanted, without you having to slog through unnecessary direct
> instatiation.  The people telling you that it doesn't work haven't updated their opinions since the mid 1990s.
> 

The code above is not equivalent to FDRSE, but this code is:

process (clk)
begin
    if rising_edge(clk) then
      if (r = '1') then
         q <= '0';
      elsif (s = '1') then
         q <= '1';
      elsif (ce = '1') then
         q <= d;
      end if;
end process;

Ed McGettigan
--
Xilinx Inc.

On Jun 20, 7:51=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> Rob Gaddi wrote:
> > On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
> > len...@gmx.de wrote:
>
> >> Rob, John thanks for reply.
>
> >>>> 2. R =3D> not R, S =3D> not S
>
> >> That's the point.
> >> Your suggestion would infer an inverter realized in a LUT.
> >> I don't want to infer extra inverter logic in the CLB. I want the
> >> inverter for free.
>
> > That's why there's a synthesis tool that's able to perform
> > optimization. =A0Last I checked, if you go back in to the FPGA Editor
> > and look in on what you've got, you'll find that XST will very
> > happily have collapsed those inverters into the free ones built into
> > the slice.
>
> > You seem to be of the opinion that it's necessary for you to outsmart
> > the synthesis tools. =A0As I said earlier, it's really rarely the case.
> > If you code:
>
> > process(clk, r, s)
> > begin
> > =A0 if (r =3D '1') then
> > =A0 =A0 q <=3D '0';
> > =A0 elsif (s =3D '1') then
> > =A0 =A0 q <=3D '1';
> > =A0 elseif rising_edge(clk) then
> > =A0 =A0 q <=3D d;
> > =A0 end if;
> > end process;
>
> > You'll find that the synthesis tool still gives you exactly what you
> > wanted, without you having to slog through unnecessary direct
> > instatiation. =A0The people telling you that it doesn't work haven't up=
dated their opinions since the mid 1990s.
>
> The code above is not equivalent to FDRSE, but this code is:
>
> process (clk)
> begin
> =A0 =A0 if rising_edge(clk) then
> =A0 =A0 =A0 if (r =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D '0';
> =A0 =A0 =A0 elsif (s =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D '1';
> =A0 =A0 =A0 elsif (ce =3D '1') then
> =A0 =A0 =A0 =A0 =A0q <=3D d;
> =A0 =A0 =A0 end if;
> end process;
>
> Ed McGettigan
> --
> Xilinx Inc.- Hide quoted text -
>
> - Show quoted text -

That code worked. It describes a FDRSE with high-active set/reset.

If you change your code to this:

 process (clk)
 begin
     if rising_edge(clk) then
       if (r =3D '0') then
          q <=3D '0';
       elsif (s =3D '0') then
          q <=3D '1';
       elsif (ce =3D '1') then
          q <=3D d;
       end if;
 end process;

it becomes a FDRSE with low-active set/reset without LUT-Logic for the
inverter.

On Fri, 19 Jun 2009 22:51:40 -0700
Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:

> Rob Gaddi wrote:
> > On Fri, 19 Jun 2009 16:59:13 -0700 (PDT)
> > lenz19@gmx.de wrote:
> > 
> >> Rob, John thanks for reply.
> >>
> >>
> >>>> 2. R => not R, S => not S
> >>
> >> That's the point.
> >> Your suggestion would infer an inverter realized in a LUT.
> >> I don't want to infer extra inverter logic in the CLB. I want the
> >> inverter for free.
> >>
> > 
> > That's why there's a synthesis tool that's able to perform
> > optimization.  Last I checked, if you go back in to the FPGA Editor
> > and look in on what you've got, you'll find that XST will very
> > happily have collapsed those inverters into the free ones built into
> > the slice.
> > 
> > You seem to be of the opinion that it's necessary for you to
> > outsmart the synthesis tools.  As I said earlier, it's really
> > rarely the case. If you code:
> > 
> > process(clk, r, s)
> > begin
> >   if (r = '1') then
> >     q <= '0';
> >   elsif (s = '1') then
> >     q <= '1';
> >   elseif rising_edge(clk) then
> >     q <= d;
> >   end if;
> > end process;
> > 
> > You'll find that the synthesis tool still gives you exactly what you
> > wanted, without you having to slog through unnecessary direct
> > instatiation.  The people telling you that it doesn't work haven't
> > updated their opinions since the mid 1990s.
> > 
> 
> The code above is not equivalent to FDRSE, but this code is:
> 
> process (clk)
> begin
>     if rising_edge(clk) then
>       if (r = '1') then
>          q <= '0';
>       elsif (s = '1') then
>          q <= '1';
>       elsif (ce = '1') then
>          q <= d;
>       end if;
> end process;
> 
> Ed McGettigan
> --
> Xilinx Inc.
> 

Good catch, you're exactly right.  I coded FDCPE instead.  Teach me to
post past five on a Friday, jacket in hand.

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order