what is a better approach to synthezise synchronous reset on FPGA?

  if Rising_Edge(Clk) then
   if RESET = '1' then
    ERROR_CODE <= (others => '0');
   elsif ENABLE = '1' then
        ...
or

  if Rising_Edge(Clk) then
   if ENABLE = '1' then
        if RESET = '1' then
            ERROR_CODE <= (others => '0');
        else
            ...

Hi Valentin,

The first one is the better way to do it.  The second will only work if your
enable is high.

Let me open another can of worms by saying 'why do you want a reset at
all?'.  Resets in *most* cases simply use up logic and routing resources
unnecessarily as all the fpga elements are initialised on powerup.  You can
even control the initialisation states of individual registers if necessary.
In *most* cases resets are mainly there to make simulations look good by
removing unknown signal conditions.

You may even miss out on some very useful resources if you automatically
apply resets to all your code... for example if you are using a Xilinx
Virtex device and you infer a shift register (i.e. 16 bits) in your HDL, you
will not be using a single SRL (Shift Register LUT) element, you will be
using 16 registers.

Food for thought ;)

Regards,


-- 
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
>   if Rising_Edge(Clk) then
>    if RESET = '1' then
>     ERROR_CODE <= (others => '0');
>    elsif ENABLE = '1' then
>         ...
> or
>
>   if Rising_Edge(Clk) then
>    if ENABLE = '1' then
>         if RESET = '1' then
>             ERROR_CODE <= (others => '0');
>         else
>             ...
>
>

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in message news:<c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de>...
> if Rising_Edge(Clk) then
>    if RESET = '1' then
>     ERROR_CODE <= (others => '0');
>    elsif ENABLE = '1' then
>         ...
> or
> 
>   if Rising_Edge(Clk) then
>    if ENABLE = '1' then
>         if RESET = '1' then
>             ERROR_CODE <= (others => '0');
>         else
>             ...

Well, quite clearly, the second will reset only if the ENABLE signal
is asserted.  Is that your desired functionality?

-a

"valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
>   if Rising_Edge(Clk) then
>    if RESET = '1' then
>     ERROR_CODE <= (others => '0');
>    elsif ENABLE = '1' then
>         ...
> or
>   if Rising_Edge(Clk) then
>    if ENABLE = '1' then
>         if RESET = '1' then
>             ERROR_CODE <= (others => '0');
>         else
>             ...

I guess it depends on what you are trying to do. The first one describes a
familiar D Flip Flop with synchronous reset and clock enable. This is the
same as  FDRE in Xilinx library. In the first case, the clock enable signal
is only required for one case. It is required if a user wants to transfer
data from the input to the output (D to Q). Clock enable signal is
irrelevant when you want to reset the flip flop. The 2nd case also describes
a similar flip flop. But in this case, the clock enable is required for both
cases. It is required if a user want to reset the flip flop and if a user
wants to transfer data from D to Q.

Hendra

> Let me open another can of worms by saying 'why do you want a reset
at
> all?'.  Resets in *most* cases simply use up logic and routing
resources
> unnecessarily as all the fpga elements are initialised on powerup.
You can
> even control the initialisation states of individual registers if
necessary.
> In *most* cases resets are mainly there to make simulations look
good by
> removing unknown signal conditions.

And when you target an ASIC? Is it ok to have registers without a
reset in an ASIC? What about the scan chain for BIST?

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

In the title of this thread - he did specifically ask about 'Synchronous
reset on FPGA'

Best Regards

-- 
Steve Merritt BEng (Hons) CEng MIEE
XILINX Gold Certified Field Applications Engineer
Insight MEMEC

Click link below for more information on :
XILINX Free Training
<http://www.xilinx.com/support/training/europe-home-page.htm>
XILINX Design Services
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
s>
10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>

Or Tel - 08707 356532 for more information



"Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
news:pyufc.448237$Or1.234590@news.chello.at...
> > Let me open another can of worms by saying 'why do you want a reset
> at
> > all?'.  Resets in *most* cases simply use up logic and routing
> resources
> > unnecessarily as all the fpga elements are initialised on powerup.
> You can
> > even control the initialisation states of individual registers if
> necessary.
> > In *most* cases resets are mainly there to make simulations look
> good by
> > removing unknown signal conditions.
>
> And when you target an ASIC? Is it ok to have registers without a
> reset in an ASIC? What about the scan chain for BIST?
>
> Martin
> --
> ----------------------------------------------
> JOP - a Java Processor core for FPGAs:
> http://www.jopdesign.com/
>
>
>

On the "can of worms"...since it is allready opened:
If you don't have a reset how you bring the FPGA logic into a known
state without power cycle?
---
jakab
"Steve Merritt" <steveb_merritt@NOSPAMhotmail.com> wrote in message
news:Keefc.123$QB3.56@newsfe5-gui.server.ntli.net...
> Hi Valentin,
>
> The first one is the better way to do it.  The second will only work if
your
> enable is high.
>
> Let me open another can of worms by saying 'why do you want a reset at
> all?'.  Resets in *most* cases simply use up logic and routing resources
> unnecessarily as all the fpga elements are initialised on powerup.  You
can
> even control the initialisation states of individual registers if
necessary.
> In *most* cases resets are mainly there to make simulations look good by
> removing unknown signal conditions.
>
> You may even miss out on some very useful resources if you automatically
> apply resets to all your code... for example if you are using a Xilinx
> Virtex device and you infer a shift register (i.e. 16 bits) in your HDL,
you
> will not be using a single SRL (Shift Register LUT) element, you will be
> using 16 registers.
>
> Food for thought ;)
>
> Regards,
>
>
> --
> Steve Merritt BEng (Hons) CEng MIEE
> XILINX Gold Certified Field Applications Engineer
> Insight MEMEC
>
> Click link below for more information on :
> XILINX Free Training
> <http://www.xilinx.com/support/training/europe-home-page.htm>
> XILINX Design Services
>
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
> s>
> 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>
>
> Or Tel - 08707 356532 for more information
>
> "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
> message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
> >   if Rising_Edge(Clk) then
> >    if RESET = '1' then
> >     ERROR_CODE <= (others => '0');
> >    elsif ENABLE = '1' then
> >         ...
> > or
> >
> >   if Rising_Edge(Clk) then
> >    if ENABLE = '1' then
> >         if RESET = '1' then
> >             ERROR_CODE <= (others => '0');
> >         else
> >             ...
> >
> >
>
>

But my question is still open ;-)

Do I need a reset for every flip-flop in an ASIC?
I want only use designs in an FPGA which are not to hard to transfer to
an ASIC. With some care only the memory models have to be exchanged and
as I know there are tools to add the BIST circuits 'on top' of the
design. Have been involved in an FPGA design that was transfered to an
ASIC, but all flip-flops where reset (there was discussion about asynch.
vs. synch reset).

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/

"Steve Merritt" <steveb_merritt@NOSPAMhotmail.com> schrieb im Newsbeitrag
news:ehvfc.339$c33.133@newsfe2-gui.server.ntli.net...
> In the title of this thread - he did specifically ask about
'Synchronous
> reset on FPGA'
>
> Best Regards
>
> --
> Steve Merritt BEng (Hons) CEng MIEE
> XILINX Gold Certified Field Applications Engineer
> Insight MEMEC
>
> Click link below for more information on :
> XILINX Free Training
> <http://www.xilinx.com/support/training/europe-home-page.htm>
> XILINX Design Services
>
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Serv
ice
> s>
> 10 Gbps Serial IO on FPGA
<http://www.xilinx.com/systemio/10gig/index.htm>
>
> Or Tel - 08707 356532 for more information
>
>
>
> "Martin Schoeberl" <martin.schoeberl@chello.at> wrote in message
> news:pyufc.448237$Or1.234590@news.chello.at...
> > > Let me open another can of worms by saying 'why do you want a reset
> > at
> > > all?'.  Resets in *most* cases simply use up logic and routing
> > resources
> > > unnecessarily as all the fpga elements are initialised on powerup.
> > You can
> > > even control the initialisation states of individual registers if
> > necessary.
> > > In *most* cases resets are mainly there to make simulations look
> > good by
> > > removing unknown signal conditions.
> >
> > And when you target an ASIC? Is it ok to have registers without a
> > reset in an ASIC? What about the scan chain for BIST?
> >
> > Martin
> > --
> > ----------------------------------------------
> > JOP - a Java Processor core for FPGAs:
> > http://www.jopdesign.com/
> >
> >
> >
>
>

You get a known state after configuration (you don't need a power up).

All flip-flops are in a defined state after configuration. But if 0 or 1
is the default state depends on your logic and synthesis tool. In Quartus
you'll get a warning when some filp-flops power up 1 (power up is
configuration). In reality all registers are cleared, but optimization
can change the logic in a way that some registers are inverted and will
be effectively 1 with respect to your original logic.

You can use this default state to generat an internal reset for some
logic without an external reset pin. E.g.:

--
-- intern reset
--
 signal int_res   : std_logic;
 signal res_cnt   : unsigned(2 downto 0);

begin

process(clk_int)
begin
 if rising_edge(clk_int) then
  if (res_cnt/="111") then
   res_cnt <= res_cnt+1;
  end if;

  int_res <= not res_cnt(0) or not res_cnt(1) or not res_cnt(2);
 end if;
end process;

With this logic res_cnt will usually be "000" after configuration, but
you have to check with simulation after P&R.

Martin
--
----------------------------------------------
JOP - a Java Processor core for FPGAs:
http://www.jopdesign.com/


"jakab tanko" <jtanko@ics-ltd.com> schrieb im Newsbeitrag
news:c5m2e4$8j$1@news.storm.ca...
> On the "can of worms"...since it is allready opened:
> If you don't have a reset how you bring the FPGA logic into a known
> state without power cycle?
> ---
> jakab
> "Steve Merritt" <steveb_merritt@NOSPAMhotmail.com> wrote in message
> news:Keefc.123$QB3.56@newsfe5-gui.server.ntli.net...
> > Hi Valentin,
> >
> > The first one is the better way to do it.  The second will only work
if
> your
> > enable is high.
> >
> > Let me open another can of worms by saying 'why do you want a reset
at
> > all?'.  Resets in *most* cases simply use up logic and routing
resources
> > unnecessarily as all the fpga elements are initialised on powerup.
You
> can
> > even control the initialisation states of individual registers if
> necessary.
> > In *most* cases resets are mainly there to make simulations look good
by
> > removing unknown signal conditions.
> >
> > You may even miss out on some very useful resources if you
automatically
> > apply resets to all your code... for example if you are using a
Xilinx
> > Virtex device and you infer a shift register (i.e. 16 bits) in your
HDL,
> you
> > will not be using a single SRL (Shift Register LUT) element, you will
be
> > using 16 registers.
> >
> > Food for thought ;)
> >
> > Regards,
> >
> >
> > --
> > Steve Merritt BEng (Hons) CEng MIEE
> > XILINX Gold Certified Field Applications Engineer
> > Insight MEMEC
> >
> > Click link below for more information on :
> > XILINX Free Training
> > <http://www.xilinx.com/support/training/europe-home-page.htm>
> > XILINX Design Services
> >
>
<http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Serv
ice
> > s>
> > 10 Gbps Serial IO on FPGA
<http://www.xilinx.com/systemio/10gig/index.htm>
> >
> > Or Tel - 08707 356532 for more information
> >
> > "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote
in
> > message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
> > >   if Rising_Edge(Clk) then
> > >    if RESET = '1' then
> > >     ERROR_CODE <= (others => '0');
> > >    elsif ENABLE = '1' then
> > >         ...
> > > or
> > >
> > >   if Rising_Edge(Clk) then
> > >    if ENABLE = '1' then
> > >         if RESET = '1' then
> > >             ERROR_CODE <= (others => '0');
> > >         else
> > >             ...
> > >
> > >
> >
> >
>
>

There is no need to reset every flip-flop in a design.  A reset signal that
breaks any feedback loops so that the design is in  a known state after some
number of clock cycles with the feedback loop and inputs forced is sufficient.
For example, a DSP design typically has a pipelined data path with little or no
feedback, and some sort of sequencer.  It is sufficient to reset the sequencer,
and hold the inputs at a known state (typically zero) long enough for any data
in the pipeline to propagate out.  If you also hold the outputs at zero while
the reset sequence is in progress, it becomes impossible to tell the difference
from outside the chip between a reset that clears every last flip-flop and one
that holds the input, output and a few key points at reset for some
predetermined length of time.  The latter doesn't chew up routing and LUT
resources the way the reset everything approach does.

jakab tanko wrote:

> On the "can of worms"...since it is allready opened:
> If you don't have a reset how you bring the FPGA logic into a known
> state without power cycle?
> ---
> jakab
> "Steve Merritt" <steveb_merritt@NOSPAMhotmail.com> wrote in message
> news:Keefc.123$QB3.56@newsfe5-gui.server.ntli.net...
> > Hi Valentin,
> >
> > The first one is the better way to do it.  The second will only work if
> your
> > enable is high.
> >
> > Let me open another can of worms by saying 'why do you want a reset at
> > all?'.  Resets in *most* cases simply use up logic and routing resources
> > unnecessarily as all the fpga elements are initialised on powerup.  You
> can
> > even control the initialisation states of individual registers if
> necessary.
> > In *most* cases resets are mainly there to make simulations look good by
> > removing unknown signal conditions.
> >
> > You may even miss out on some very useful resources if you automatically
> > apply resets to all your code... for example if you are using a Xilinx
> > Virtex device and you infer a shift register (i.e. 16 bits) in your HDL,
> you
> > will not be using a single SRL (Shift Register LUT) element, you will be
> > using 16 registers.
> >
> > Food for thought ;)
> >
> > Regards,
> >
> >
> > --
> > Steve Merritt BEng (Hons) CEng MIEE
> > XILINX Gold Certified Field Applications Engineer
> > Insight MEMEC
> >
> > Click link below for more information on :
> > XILINX Free Training
> > <http://www.xilinx.com/support/training/europe-home-page.htm>
> > XILINX Design Services
> >
> <http://www.xilinx.com/xlnx/xil_prodcat_landingpage.jsp?title=Design+Service
> > s>
> > 10 Gbps Serial IO on FPGA <http://www.xilinx.com/systemio/10gig/index.htm>
> >
> > Or Tel - 08707 356532 for more information
> >
> > "valentin tihomirov" <valentin_NOSPAM_NOWORMS@abelectron.com> wrote in
> > message news:c5j6rg$2bkqr$1@ID-212430.news.uni-berlin.de...
> > >   if Rising_Edge(Clk) then
> > >    if RESET = '1' then
> > >     ERROR_CODE <= (others => '0');
> > >    elsif ENABLE = '1' then
> > >         ...
> > > or
> > >
> > >   if Rising_Edge(Clk) then
> > >    if ENABLE = '1' then
> > >         if RESET = '1' then
> > >             ERROR_CODE <= (others => '0');
> > >         else
> > >             ...
> > >
> > >
> >
> >

--
--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
401/884-7930     Fax 401/884-7950
email ray@andraka.com
http://www.andraka.com

 "They that give up essential liberty to obtain a little
  temporary safety deserve neither liberty nor safety."
                                          -Benjamin Franklin, 1759