Generating a negated clock

Hi all,
I'm using a Virtex4.

My project uses several clock generated by a DCM wich receive the
external 100MHz.

For every of this clock I need the clock and its negated version. DCM
gives 180� version of almost every output but not for the CLKDIV output.
Is possible to generate in a simple way a negated clock and have it
recognized by the syntesizer (ISE8.2) like a real clock?

For example is it possible to use just a not port and put the exit in a
clock buffer?

Regards.
-- 
Accomplishing the impossible means only that the boss will add it to
your regular duties.
 _  _                  _
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"Nemesis" <nemesis@nowhere.invalid> wrote in message 
news:20090709204834.4086.18180.XPN@orion.invalid...
> Hi all,
> I'm using a Virtex4.
>
> My project uses several clock generated by a DCM wich receive the
> external 100MHz.
>
> For every of this clock I need the clock and its negated version. DCM
> gives 180&#4294967295; version of almost every output but not for the CLKDIV output.
> Is possible to generate in a simple way a negated clock and have it
> recognized by the syntesizer (ISE8.2) like a real clock?
>
> For example is it possible to use just a not port and put the exit in a
> clock buffer?

Slices can be configured to work on either edge.  You can use a mixture of:

always @ (posedge clk)
always @ (negedge clk)

and only one global clock resource is used.

On Jul 9, 11:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote:
> "Nemesis" <neme...@nowhere.invalid> wrote in message
>
> news:20090709204834.4086.18180.XPN@orion.invalid...
>
> > Hi all,
> > I'm using a Virtex4.
>
> > My project uses several clock generated by a DCM wich receive the
> > external 100MHz.
>
> > For every of this clock I need the clock and its negated version. DCM
> > gives 180=B0 version of almost every output but not for the CLKDIV outp=
ut.
> > Is possible to generate in a simple way a negated clock and have it
> > recognized by the syntesizer (ISE8.2) like a real clock?
>
> > For example is it possible to use just a not port and put the exit in a
> > clock buffer?
>
> Slices can be configured to work on either edge. =A0You can use a mixture=
 of:
>
> always @ (posedge clk)
> always @ (negedge clk)
>
> and only one global clock resource is used.

I'm not sure to understand.
Both clocks (CLK and CLK180) are required by a FIFO module.

On 10 July, 11:17, Nemesis <gnemesis2...@gmail.com> wrote:
> On Jul 9, 11:43=A0pm, "Andrew Holme" <a...@nospam.co.uk> wrote:
>
>
>
> > "Nemesis" <neme...@nowhere.invalid> wrote in message
>
> >news:20090709204834.4086.18180.XPN@orion.invalid...
>
> > > Hi all,
> > > I'm using a Virtex4.
>
> > > My project uses several clock generated by a DCM wich receive the
> > > external 100MHz.
>
> > > For every of this clock I need the clock and its negated version. DCM
> > > gives 180=B0 version of almost every output but not for the CLKDIV ou=
tput.
> > > Is possible to generate in a simple way a negated clock and have it
> > > recognized by the syntesizer (ISE8.2) like a real clock?
>
> > > For example is it possible to use just a not port and put the exit in=
 a
> > > clock buffer?
>
> > Slices can be configured to work on either edge. =A0You can use a mixtu=
re of:
>
> > always @ (posedge clk)
> > always @ (negedge clk)
>
> > and only one global clock resource is used.
>
> I'm not sure to understand.
> Both clocks (CLK and CLK180) are required by a FIFO module.

What happens if you connect clk and ~clk to the true and negated clock
ports?  I think it will route the one global clock net to all slices
in the FIFO and configure some as rising edge sensitive and some as
falling edge sensitive.

"Nemesis" <gnemesis2001@gmail.com> wrote
>
> Both clocks (CLK and CLK180) are required by a FIFO module.

Which FIFO module?


/Mikhail 

MM wrote:

> "Nemesis" <gnemesis2001@gmail.com> wrote
>>
>> Both clocks (CLK and CLK180) are required by a FIFO module.
>
> Which FIFO module?

I'm using a module written by the vendor of the boards that mounts the
FPGA.

-- 
I told my psychiatrist that everyone hates me. He said I was being
ridiculous - everyone hasn't met me yet.
 _  _                  _
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"Nemesis" <nemesis@nowhere.invalid> wrote
>
> I'm using a module written by the vendor of the boards that mounts the
> FPGA.
>

1. Why don't you use Xilinx core? It will work happily with a single clock.
2. If you really need to invert a DCM CLKDIV clock it you can use a second 
DCM.

Also, take a look at the PMCD (Phase-Matched Clock Divider) V4 primitive.


/Mikhail 

MM wrote:

>> I'm using a module written by the vendor of the boards that mounts the
>> FPGA.
> 1. Why don't you use Xilinx core? It will work happily with a single clock.
> 2. If you really need to invert a DCM CLKDIV clock it you can use a second 
> DCM.

I interfaced my DSP code with base code of the board (an ADC board).
I don't want to modify the original code. I think they didn't use the
Xilinx core because the fifo's depth is about 12000, Xilinx core accept
only power of 2 depths if I remember well.

> Also, take a look at the PMCD (Phase-Matched Clock Divider) V4 primitive.

I will, thanks.
-- 
I may not have gone where I intended to go, but I think I have ended up
where I needed to be.
 _  _                  _
| \| |___ _ __  ___ __(_)___
| .` / -_) '  \/ -_|_-< (_-<
|_|\_\___|_|_|_\___/__/_/__/ http://xpn.altervista.org

On Jul 16, 11:41=A0am, Nemesis <neme...@nowhere.invalid> wrote:
> MM wrote:
> >> I'm using a module written by the vendor of the boards that mounts the
> >> FPGA.
> > 1. Why don't you use Xilinx core? It will work happily with a single cl=
ock.
> > 2. If you really need to invert a DCM CLKDIV clock it you can use a sec=
ond
> > DCM.
>
> I interfaced my DSP code with base code of the board (an ADC board).
> I don't want to modify the original code. I think they didn't use the
> Xilinx core because the fifo's depth is about 12000, Xilinx core accept
> only power of 2 depths if I remember well.
>
I have never seen an application where the exact FIFO depth value was
critical, as long as it was deep enough.
Also, there is the ALMOST FULL flag that can be set to any value.
Peter Alfke, Xilinx

On Jul 16, 2:48=A0pm, Peter Alfke <pe...@xilinx.com> wrote:
> On Jul 16, 11:41=A0am, Nemesis <neme...@nowhere.invalid> wrote:> MM wrote=
:
> > >> I'm using a module written by the vendor of the boards that mounts t=
he
> > >> FPGA.
> > > 1. Why don't you use Xilinx core? It will work happily with a single =
clock.
> > > 2. If you really need to invert a DCM CLKDIV clock it you can use a s=
econd
> > > DCM.
>
> > I interfaced my DSP code with base code of the board (an ADC board).
> > I don't want to modify the original code. I think they didn't use the
> > Xilinx core because the fifo's depth is about 12000, Xilinx core accept
> > only power of 2 depths if I remember well.
>
> I have never seen an application where the exact FIFO depth value was
> critical, as long as it was deep enough.
> Also, there is the ALMOST FULL flag that can be set to any value.
> Peter Alfke, Xilinx

The point is that deep enough is often not a power of two and you
may not have the block RAM to waste on the unused portion.  The
control circuitry would obviously be the same size since you
haven't reduced the number of address bits.