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Xilinx Spartan 3 DCM no output!

Started by muse_ee ●July 10, 2009
Hi, I'm trying to learn how to use the DCM's frequency synthesis capability
to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. I
used Xilinx Architecture wizard to generate the code and the clock
multiplication works correctly in timing simulation. When I get to the
bench to test however, I don't get a multiplied clock output - the line is
0. I have a couple debug signals that tell me the following:

-75MHz, post BUFG looks fine (I see output from the FPGA)
-DCM Lock is 0 
-Status(2 downto 0) are all 0.

I've tried the design on 2 different boards, ruling out defective
hardware. I'm really scratching my head here so I'd greatly appreciate some
help from a Xilinx guru!


Here is my VHDL for the clock multiplier (well, more accurately Xilinx's
VHDL):
   GND_BIT <= '0';
   CLKIN_IBUFG_OUT <= CLKIN_IBUFG;
   CLKFX_BUFG_INST : BUFG
      port map (I=>CLKFX_BUF,
                O=>CLKFX_OUT);
   
   CLKIN_IBUFG_INST : IBUFG
      port map (I=>CLKIN_IN,
                O=>CLKIN_IBUFG);
   
   DCM_INST : DCM
   generic map( CLK_FEEDBACK => "NONE",
            CLKDV_DIVIDE => 2.0,
            CLKFX_DIVIDE => 4,
            CLKFX_MULTIPLY => 5,
            CLKIN_DIVIDE_BY_2 => FALSE,
            CLKIN_PERIOD => 12.500,
            CLKOUT_PHASE_SHIFT => "NONE",
            DESKEW_ADJUST => "SYSTEM_SYNCHRONOUS",
            DFS_FREQUENCY_MODE => "LOW",
            DLL_FREQUENCY_MODE => "LOW",
            DUTY_CYCLE_CORRECTION => TRUE,
            FACTORY_JF => x"8080",
            PHASE_SHIFT => 0,
            STARTUP_WAIT => FALSE)
      port map (CLKFB=>GND_BIT,
                CLKIN=>CLKIN_IBUFG,
                DSSEN=>GND_BIT,
                PSCLK=>GND_BIT,
                PSEN=>GND_BIT,
                PSINCDEC=>GND_BIT,
                RST=>RST_IN,
                CLKDV=>open,
                CLKFX=>CLKFX_BUF,
                CLKFX180=>open,
                CLK0=>open,
                CLK2X=>open,
                CLK2X180=>open,
                CLK90=>open,
                CLK180=>open,
                CLK270=>open,
                LOCKED=>LOCKED_OUT,
                PSDONE=>open,
                STATUS(7 downto 0)=>STATUS_OUT(7 downto 0));
Reply by ●July 10, 20092009-07-10
Hi,
You just have to feedback the CLK0 to CLKFB! otherwise the DLL will
not lock :)

On Jul 10, 4:40=A0pm, "muse_ee" <brian.bubn...@jhuapl.edu> wrote:

> Hi, I'm trying to learn how to use the DCM's frequency synthesis capabili=

ty

> to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. =

I

> used Xilinx Architecture wizard to generate the code and the clock
> multiplication works correctly in timing simulation. When I get to the
> bench to test however, I don't get a multiplied clock output - the line i=

s

> 0. I have a couple debug signals that tell me the following:
>
> -75MHz, post BUFG looks fine (I see output from the FPGA)
> -DCM Lock is 0
> -Status(2 downto 0) are all 0.
>
> I've tried the design on 2 different boards, ruling out defective
> hardware. I'm really scratching my head here so I'd greatly appreciate so=

me

> help from a Xilinx guru!
>
> Here is my VHDL for the clock multiplier (well, more accurately Xilinx's
> VHDL):
> =A0 =A0GND_BIT <=3D '0';
> =A0 =A0CLKIN_IBUFG_OUT <=3D CLKIN_IBUFG;
> =A0 =A0CLKFX_BUFG_INST : BUFG
> =A0 =A0 =A0 port map (I=3D>CLKFX_BUF,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKFX_OUT);
>
> =A0 =A0CLKIN_IBUFG_INST : IBUFG
> =A0 =A0 =A0 port map (I=3D>CLKIN_IN,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKIN_IBUFG);
>
> =A0 =A0DCM_INST : DCM
> =A0 =A0generic map( CLK_FEEDBACK =3D> "NONE",
> =A0 =A0 =A0 =A0 =A0 =A0 CLKDV_DIVIDE =3D> 2.0,
> =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_DIVIDE =3D> 4,
> =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_MULTIPLY =3D> 5,
> =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_DIVIDE_BY_2 =3D> FALSE,
> =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_PERIOD =3D> 12.500,
> =A0 =A0 =A0 =A0 =A0 =A0 CLKOUT_PHASE_SHIFT =3D> "NONE",
> =A0 =A0 =A0 =A0 =A0 =A0 DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS",
> =A0 =A0 =A0 =A0 =A0 =A0 DFS_FREQUENCY_MODE =3D> "LOW",
> =A0 =A0 =A0 =A0 =A0 =A0 DLL_FREQUENCY_MODE =3D> "LOW",
> =A0 =A0 =A0 =A0 =A0 =A0 DUTY_CYCLE_CORRECTION =3D> TRUE,
> =A0 =A0 =A0 =A0 =A0 =A0 FACTORY_JF =3D> x"8080",
> =A0 =A0 =A0 =A0 =A0 =A0 PHASE_SHIFT =3D> 0,
> =A0 =A0 =A0 =A0 =A0 =A0 STARTUP_WAIT =3D> FALSE)
> =A0 =A0 =A0 port map (CLKFB=3D>GND_BIT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKIN=3D>CLKIN_IBUFG,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DSSEN=3D>GND_BIT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSCLK=3D>GND_BIT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSEN=3D>GND_BIT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSINCDEC=3D>GND_BIT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RST=3D>RST_IN,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX=3D>CLKFX_BUF,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX180=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK0=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X180=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK180=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK270=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOCKED=3D>LOCKED_OUT,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSDONE=3D>open,
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 STATUS(7 downto 0)=3D>STATUS_OUT(7 downto=

 0));
Reply by muse_ee ●July 11, 20092009-07-11
On Jul 10, 12:45=A0pm, [LinuxF8-64]GaLaKtIkUs=99 <taileb.me...@gmail.com>
wrote:

> Hi,
> You just have to feedback the CLK0 to CLKFB! otherwise the DLL will
> not lock :)
>
> On Jul 10, 4:40=A0pm, "muse_ee" <brian.bubn...@jhuapl.edu> wrote:
>
>
>
> > Hi, I'm trying to learn how to use the DCM's frequency synthesis capabi=

lity

> > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock=

. I

> > used Xilinx Architecture wizard to generate the code and the clock
> > multiplication works correctly in timing simulation. When I get to the
> > bench to test however, I don't get a multiplied clock output - the line=

 is

> > 0. I have a couple debug signals that tell me the following:
>
> > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > -DCM Lock is 0
> > -Status(2 downto 0) are all 0.
>
> > I've tried the design on 2 different boards, ruling out defective
> > hardware. I'm really scratching my head here so I'd greatly appreciate =

some

> > help from a Xilinx guru!
>
> > Here is my VHDL for the clock multiplier (well, more accurately Xilinx'=

s

> > VHDL):
> > =A0 =A0GND_BIT <=3D '0';
> > =A0 =A0CLKIN_IBUFG_OUT <=3D CLKIN_IBUFG;
> > =A0 =A0CLKFX_BUFG_INST : BUFG
> > =A0 =A0 =A0 port map (I=3D>CLKFX_BUF,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKFX_OUT);
>
> > =A0 =A0CLKIN_IBUFG_INST : IBUFG
> > =A0 =A0 =A0 port map (I=3D>CLKIN_IN,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 O=3D>CLKIN_IBUFG);
>
> > =A0 =A0DCM_INST : DCM
> > =A0 =A0generic map( CLK_FEEDBACK =3D> "NONE",
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKDV_DIVIDE =3D> 2.0,
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_DIVIDE =3D> 4,
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKFX_MULTIPLY =3D> 5,
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_DIVIDE_BY_2 =3D> FALSE,
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKIN_PERIOD =3D> 12.500,
> > =A0 =A0 =A0 =A0 =A0 =A0 CLKOUT_PHASE_SHIFT =3D> "NONE",
> > =A0 =A0 =A0 =A0 =A0 =A0 DESKEW_ADJUST =3D> "SYSTEM_SYNCHRONOUS",
> > =A0 =A0 =A0 =A0 =A0 =A0 DFS_FREQUENCY_MODE =3D> "LOW",
> > =A0 =A0 =A0 =A0 =A0 =A0 DLL_FREQUENCY_MODE =3D> "LOW",
> > =A0 =A0 =A0 =A0 =A0 =A0 DUTY_CYCLE_CORRECTION =3D> TRUE,
> > =A0 =A0 =A0 =A0 =A0 =A0 FACTORY_JF =3D> x"8080",
> > =A0 =A0 =A0 =A0 =A0 =A0 PHASE_SHIFT =3D> 0,
> > =A0 =A0 =A0 =A0 =A0 =A0 STARTUP_WAIT =3D> FALSE)
> > =A0 =A0 =A0 port map (CLKFB=3D>GND_BIT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKIN=3D>CLKIN_IBUFG,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 DSSEN=3D>GND_BIT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSCLK=3D>GND_BIT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSEN=3D>GND_BIT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSINCDEC=3D>GND_BIT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 RST=3D>RST_IN,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKDV=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX=3D>CLKFX_BUF,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLKFX180=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK0=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK2X180=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK90=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK180=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 CLK270=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LOCKED=3D>LOCKED_OUT,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 PSDONE=3D>open,
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 STATUS(7 downto 0)=3D>STATUS_OUT(7 down=

to 0));

Alright, I tried adding a feedback signal between CLK0 and CLKFB, and
changed the CLK_FEEDBACK attribute from "None" to "1X". This didn't
have any effect.
Reply by Martin Thompson ●July 13, 20092009-07-13
"muse_ee" <brian.bubnash@jhuapl.edu> writes:


> Hi, I'm trying to learn how to use the DCM's frequency synthesis capability
> to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock. I
> used Xilinx Architecture wizard to generate the code and the clock
> multiplication works correctly in timing simulation. When I get to the
> bench to test however, I don't get a multiplied clock output - the line is
> 0. I have a couple debug signals that tell me the following:
>
> -75MHz, post BUFG looks fine (I see output from the FPGA)
> -DCM Lock is 0 
> -Status(2 downto 0) are all 0.


One thought - what does your reset to the DCM look like?  It has a
minimum pulse length documented in the datasheet for the part.

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html
Reply by muse_ee ●July 13, 20092009-07-13
On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:

> "muse_ee" <brian.bubn...@jhuapl.edu> writes:
> > Hi, I'm trying to learn how to use the DCM's frequency synthesis capabi=

lity

> > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock=

. I

> > used Xilinx Architecture wizard to generate the code and the clock
> > multiplication works correctly in timing simulation. When I get to the
> > bench to test however, I don't get a multiplied clock output - the line=

 is

> > 0. I have a couple debug signals that tell me the following:
>
> > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > -DCM Lock is 0
> > -Status(2 downto 0) are all 0.
>
> One thought - what does your reset to the DCM look like? =A0It has a
> minimum pulse length documented in the datasheet for the part.
>
> Cheers,
> Martin
>
> --
> martin.j.thomp...@trw.com
> TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp://w=

ww.conekt.net/electronics.html

Thanks for the reply - I saw the minimum pulse length requirements and
so I put this reset pulse extender in. It ensures that any pulse
coming from the reset button lasts for at least 256 clock cycles
(overkill I know but this was put in well past the point of
desperation). I have tried pressing the reset button several minutes
after powering the FPGA to see if the clock was slow to stabilize for
some reason, but nothing I do seems to make the output from the DCM
vary from '0'. Below is my reset manager code:

	rst_manager : process(clk,rstn)
		variable cnt : std_logic_vector(7 downto 0);
		variable r : std_logic;
		constant ones : std_logic_vector(7 downto 0) :=3D (others =3D> '1');
	begin
		r :=3D not rstn;
		if r =3D '1' then
			cnt :=3D (others =3D> '0');
			rst <=3D '1';
		elsif rising_edge(clk) then
			if cnt =3D ones then
				rst <=3D '0';
			else
				rst <=3D '1';
				cnt :=3D cnt + '1';
			end if;
		end if;
	end process;
Reply by gabor ●July 13, 20092009-07-13
On Jul 13, 10:05=A0am, muse_ee <brian.bubn...@gmail.com> wrote:

> On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
>
>
> > "muse_ee" <brian.bubn...@jhuapl.edu> writes:
> > > Hi, I'm trying to learn how to use the DCM's frequency synthesis capa=

bility

> > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clo=

ck. I

> > > used Xilinx Architecture wizard to generate the code and the clock
> > > multiplication works correctly in timing simulation. When I get to th=

e

> > > bench to test however, I don't get a multiplied clock output - the li=

ne is

> > > 0. I have a couple debug signals that tell me the following:
>
> > > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > > -DCM Lock is 0
> > > -Status(2 downto 0) are all 0.
>
> > One thought - what does your reset to the DCM look like? =A0It has a
> > minimum pulse length documented in the datasheet for the part.
>
> > Cheers,
> > Martin
>
> > --
> > martin.j.thomp...@trw.com
> > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp:/=

/www.conekt.net/electronics.html

>
> Thanks for the reply - I saw the minimum pulse length requirements and
> so I put this reset pulse extender in. It ensures that any pulse
> coming from the reset button lasts for at least 256 clock cycles
> (overkill I know but this was put in well past the point of
> desperation). I have tried pressing the reset button several minutes
> after powering the FPGA to see if the clock was slow to stabilize for
> some reason, but nothing I do seems to make the output from the DCM
> vary from '0'. Below is my reset manager code:
>
> =A0 =A0 =A0 =A0 rst_manager : process(clk,rstn)
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable cnt : std_logic_vector(7 downto =

0);

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r : std_logic;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 constant ones : std_logic_vector(7 downto=

 0) :=3D (others =3D> '1');

> =A0 =A0 =A0 =A0 begin
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D not rstn;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r =3D '1' then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D (others =3D> '0'=

);

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if cnt =3D ones then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D =

'0';

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D =

'1';

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D =

cnt + '1';

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end process;


What is your clock source?  Are you sure it meets the input
jitter requirements and frequency range requirements?
Reply by muse_ee ●July 13, 20092009-07-13
On Jul 13, 10:26=A0am, gabor <ga...@alacron.com> wrote:

> On Jul 13, 10:05=A0am, muse_ee <brian.bubn...@gmail.com> wrote:
>
>
>
> > On Jul 13, 3:45=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote=

:

>
> > > "muse_ee" <brian.bubn...@jhuapl.edu> writes:
> > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis ca=

pability

> > > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz c=

lock. I

> > > > used Xilinx Architecture wizard to generate the code and the clock
> > > > multiplication works correctly in timing simulation. When I get to =

the

> > > > bench to test however, I don't get a multiplied clock output - the =

line is

> > > > 0. I have a couple debug signals that tell me the following:
>
> > > > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > > > -DCM Lock is 0
> > > > -Status(2 downto 0) are all 0.
>
> > > One thought - what does your reset to the DCM look like? =A0It has a
> > > minimum pulse length documented in the datasheet for the part.
>
> > > Cheers,
> > > Martin
>
> > > --
> > > martin.j.thomp...@trw.com
> > > TRW Conekt - Consultancy in Engineering, Knowledge and Technologyhttp=

://www.conekt.net/electronics.html

>
> > Thanks for the reply - I saw the minimum pulse length requirements and
> > so I put this reset pulse extender in. It ensures that any pulse
> > coming from the reset button lasts for at least 256 clock cycles
> > (overkill I know but this was put in well past the point of
> > desperation). I have tried pressing the reset button several minutes
> > after powering the FPGA to see if the clock was slow to stabilize for
> > some reason, but nothing I do seems to make the output from the DCM
> > vary from '0'. Below is my reset manager code:
>
> > =A0 =A0 =A0 =A0 rst_manager : process(clk,rstn)
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable cnt : std_logic_vector(7 downt=

o 0);

> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 variable r : std_logic;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 constant ones : std_logic_vector(7 down=

to 0) :=3D (others =3D> '1');

> > =A0 =A0 =A0 =A0 begin
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 r :=3D not rstn;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if r =3D '1' then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=3D (others =3D> '=

0');

> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=3D '1';
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif rising_edge(clk) then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if cnt =3D ones then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=

=3D '0';

> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 rst <=

=3D '1';

> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 cnt :=

=3D cnt + '1';

> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> > =A0 =A0 =A0 =A0 end process;
>
> What is your clock source? =A0Are you sure it meets the input
> jitter requirements and frequency range requirements?


Thanks for the suggestion. I checked and clock source is a 75MHz
Pletronics clock oscillator, SM7745DW (jitter under 3pS RMS according
to datasheet). I believe that both parameters are within their
acceptable ranges.
Reply by MikeWhy ●July 13, 20092009-07-13
"muse_ee" <brian.bubnash@gmail.com> wrote in message 
news:b9b61f51-2f7b-4b3e-a2b3-58848f6ffb06@n30g2000vba.googlegroups.com...
On Jul 13, 10:26 am, gabor <ga...@alacron.com> wrote:

> On Jul 13, 10:05 am, muse_ee <brian.bubn...@gmail.com> wrote:
>
>
>
> > On Jul 13, 3:45 am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
> > > "muse_ee" <brian.bubn...@jhuapl.edu> writes:
> > > > Hi, I'm trying to learn how to use the DCM's frequency synthesis 
> > > > capability
> > > > to convert a 75MHz clock (on-board oscillator chip) into a 100MHz 
> > > > clock. I
> > > > used Xilinx Architecture wizard to generate the code and the clock
> > > > multiplication works correctly in timing simulation. When I get to 
> > > > the
> > > > bench to test however, I don't get a multiplied clock output - the 
> > > > line is
> > > > 0. I have a couple debug signals that tell me the following:
>
> > > > -75MHz, post BUFG looks fine (I see output from the FPGA)
> > > > -DCM Lock is 0
> > > > -Status(2 downto 0) are all 0.
>
> > > One thought - what does your reset to the DCM look like? It has a
> > > minimum pulse length documented in the datasheet for the part.
>
> > > Cheers,
> > > Martin
>
> > > --
> > > martin.j.thomp...@trw.com
> > > TRW Conekt - Consultancy in Engineering, Knowledge and 
> > > Technologyhttp://www.conekt.net/electronics.html
>
> > Thanks for the reply - I saw the minimum pulse length requirements and
> > so I put this reset pulse extender in. It ensures that any pulse
> > coming from the reset button lasts for at least 256 clock cycles
> > (overkill I know but this was put in well past the point of
> > desperation). I have tried pressing the reset button several minutes
> > after powering the FPGA to see if the clock was slow to stabilize for
> > some reason, but nothing I do seems to make the output from the DCM
> > vary from '0'. Below is my reset manager code:
>
> > rst_manager : process(clk,rstn)
> > variable cnt : std_logic_vector(7 downto 0);
> > variable r : std_logic;
> > constant ones : std_logic_vector(7 downto 0) := (others => '1');
> > begin
> > r := not rstn;
> > if r = '1' then
> > cnt := (others => '0');
> > rst <= '1';
> > elsif rising_edge(clk) then
> > if cnt = ones then
> > rst <= '0';
> > else
> > rst <= '1';
> > cnt := cnt + '1';
> > end if;
> > end if;
> > end process;
>
> What is your clock source? Are you sure it meets the input
> jitter requirements and frequency range requirements?


Thanks for the suggestion. I checked and clock source is a 75MHz
Pletronics clock oscillator, SM7745DW (jitter under 3pS RMS according
to datasheet). I believe that both parameters are within their
acceptable ranges.

=======
Did you see the earlier message regarding tying CLK_FB to CLK_0? UG331 
states: "The feedback input is required unless the Digital Frequency 
Synthesis outputs, CLKFX or CLKFX180, are used stand-alone." You do need the 
feedback if you're using the DLL. (I don't recall your relevant details, 
though.)
Reply by alan...@nishioka.com ●July 13, 20092009-07-13
On Jul 10, 5:40=A0am, "muse_ee" <brian.bubn...@jhuapl.edu> wrote:

> Hi, I'm trying to learn how to use the DCM's frequency synthesis capabili=

ty

> to convert a 75MHz clock (on-board oscillator chip) into a 100MHz clock.
>
> I've tried the design on 2 different boards, ruling out defective
> hardware. I'm really scratching my head here so I'd greatly appreciate so=

me

> help from a Xilinx guru!


have you looked at the design with fpga_editor to verify everything
looks right?
have you checked that the pin you are looking at can toggle?
(*i've* never made a hw error, but i've heard it is possible)
is this a custom board or off the shelf hw?
perhaps you should post the entire vhdl file and ucf file.  there may
be something wrong elsewhere.
Reply by Martin Thompson ●July 14, 20092009-07-14
muse_ee <brian.bubnash@gmail.com> writes:


> Thanks for the reply - I saw the minimum pulse length requirements and
> so I put this reset pulse extender in. It ensures that any pulse
> coming from the reset button lasts for at least 256 clock cycles
> (overkill I know but this was put in well past the point of
> desperation). I have tried pressing the reset button several minutes
> after powering the FPGA to see if the clock was slow to stabilize for
> some reason, but nothing I do seems to make the output from the DCM
> vary from '0'. Below is my reset manager code:


I assume you're using the "raw" clock to clock this process, not the
(as-yet-non-existent) one from the DCM...  I've heard that's a possible
mistake to make, but obviously I've never done it myself (not a 2nd time
anyway :)

Can you bring your extended reset out to a pin to check it?

The idea of looking with FPGA editor is also a good one.  And check the
feedback!

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html