Master initialization problem with xilinx 32 bit pci master/target ipcore

I am using 32 bit PCI master/target ipcore from Xilinx.
Xilinx ISE10.1.
http://www.xilinx.com/support/documentation/ip_documentation/pci_64_ug159.pdf


My problem is,  My user application(PCI IP core’s) should be the Master
and when it is trying to request 
the PCI bus, I found a situation that, I have to enable the master bit in
Command register(CSR2).
I tried the initiator write and self configuration write steps from the
pci tutorial, but I can not write into the command register.

When I generate the core from the IP Coregen, I have access to the
configuration space, like
Device ID, Base address registers etc. But I can not access Command
Register.

Can any one please tell me how can I initiate the master? Or Is there any
other way?

Thank you.