FPGA to PC connection

hey guys,

I have an FPGA capturing binarizing an image and want to connect it to
a PC for further analysis etc. What do you think would be the best
protocol to use? The data itself is about 12.8 Mbits/second so was
leaning toward 100Mbps ethernet implemented on the FPGA. Is this
possible (plausible) without a soft processor, ie: just streaming the
images straight from the FPGA RAM? Any links to relevant readings
would be greatly appreciated so I could learn.

G

Gints <reganireland@gmail.com> wrote:
> hey guys,

> I have an FPGA capturing binarizing an image and want to connect it to
> a PC for further analysis etc. What do you think would be the best
> protocol to use? The data itself is about 12.8 Mbits/second so was
> leaning toward 100Mbps ethernet implemented on the FPGA. Is this
> possible (plausible) without a soft processor, ie: just streaming the
> images straight from the FPGA RAM? Any links to relevant readings
> would be greatly appreciated so I could learn.

FT2232H (Only software on the PC side)
or 
Cypress FX2 (Cy7C68013) (FX2 and PC programming needed)
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Gints <reganireland@gmail.com> wrote:
 
> I have an FPGA capturing binarizing an image and want to connect it to
> a PC for further analysis etc. What do you think would be the best
> protocol to use? The data itself is about 12.8 Mbits/second so was
> leaning toward 100Mbps ethernet implemented on the FPGA. Is this
> possible (plausible) without a soft processor, ie: just streaming the
> images straight from the FPGA RAM? Any links to relevant readings
> would be greatly appreciated so I could learn.

Depending on your definition of 'soft processor.'

You will need a state machine of some kind, which may or 
may not be considered a processor.

-- glen

Gints wrote:

> hey guys,
> 
> I have an FPGA capturing binarizing an image and want to connect it to
> a PC for further analysis etc. What do you think would be the best
> protocol to use? The data itself is about 12.8 Mbits/second so was
> leaning toward 100Mbps ethernet implemented on the FPGA. Is this
> possible (plausible) without a soft processor, ie: just streaming the
> images straight from the FPGA RAM? Any links to relevant readings
> would be greatly appreciated so I could learn.
> 
> G

This is certainly reasonable if you use UDP. If you only implement
ARP and UDP, the interface with a PHY chip is straighforward.
There is an example of a 10Mbps aat www.fpga4fun.com. I did a
100Mbps interface without a processor for a data collection
system.

doug <xx@xx.com> wrote:


> Gints wrote:

> > hey guys,
> > 
> > I have an FPGA capturing binarizing an image and want to connect it to
> > a PC for further analysis etc. What do you think would be the best
> > protocol to use? The data itself is about 12.8 Mbits/second so was
> > leaning toward 100Mbps ethernet implemented on the FPGA. Is this
> > possible (plausible) without a soft processor, ie: just streaming the
> > images straight from the FPGA RAM? Any links to relevant readings
> > would be greatly appreciated so I could learn.
> > 
> > G

> This is certainly reasonable if you use UDP. If you only implement
> ARP and UDP, the interface with a PHY chip is straighforward.
> There is an example of a 10Mbps aat www.fpga4fun.com. I did a
> 100Mbps interface without a processor for a data collection
> system.

Are you willing to share?
-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Uwe Bonnes wrote:

> doug <xx@xx.com> wrote:
> 
> 
> 
>>Gints wrote:
> 
> 
>>>hey guys,
>>>
>>>I have an FPGA capturing binarizing an image and want to connect it to
>>>a PC for further analysis etc. What do you think would be the best
>>>protocol to use? The data itself is about 12.8 Mbits/second so was
>>>leaning toward 100Mbps ethernet implemented on the FPGA. Is this
>>>possible (plausible) without a soft processor, ie: just streaming the
>>>images straight from the FPGA RAM? Any links to relevant readings
>>>would be greatly appreciated so I could learn.
>>>
>>>G
> 
> 
>>This is certainly reasonable if you use UDP. If you only implement
>>ARP and UDP, the interface with a PHY chip is straighforward.
>>There is an example of a 10Mbps aat www.fpga4fun.com. I did a
>>100Mbps interface without a processor for a data collection
>>system.
> 
> 
> Are you willing to share?

Unfortunately this was done for a customer who does not want it
released.  But the basic idea is that you need to respond to the
ARP so that a switch knows the MAC address that corresponds to
the IP the PC is asking for. The phy chip gives the data in 4 bit
nibbles so that needs to be made to 8 bit bytes for easier
processing.   I process the packet as it comes through with an
address detector and then a data processor.  The replies are a
bit of a nuisance since the checksum for the data is in the
header and, in a streaming data situation, the data comes out
afterwards.  There are two solutions to this. One is to put
the data in a fifo and calculate the checksum as it comes
in and have the packet header stored in a separate block.
This way for repeated data, the header only needs to be
setup once.  The second way to deal with the checksum
is to set it to zero, in which case, the PC ignores it.
UDP is nice since it is a send and forget protocol. Particularly
for local transmission, there is no need for the extra
abilities and overhead of a TCP connection.  We have run the
system all day without losing a packet so the retries are
not so important.

The biggest nuisance of the whole deal was getting the CRC correct.
There are online CRC calculators but troubleshooting that part is
a real pain. If the CRC is wrong, the PC will not see anything
so you cannot even get to see what it thought the value should be.
(The checksum values are reported in Wireshark and tell you what
the correct value is if you have made a mistake).

Gints :
> hey guys,
> I have an FPGA capturing binarizing an image and want to connect it to
> a PC for further analysis etc. What do you think would be the best
> protocol to use? The data itself is about 12.8 Mbits/second so was
> leaning toward 100Mbps ethernet implemented on the FPGA. Is this
> possible (plausible) without a soft processor, ie: just streaming the
> images straight from the FPGA RAM? Any links to relevant readings
> would be greatly appreciated so I could learn.

Hi,

We do have developed a module doing just this (streaming data both ways 
through Ethernet). No processor, no SW stack, no external memory, no 
MAC, no SGDMA, no RTOS... all is included in our very compact IP, 
including the PC side SW.
Note that it is affordable but it's NOT free.

12.8 Mbits is :
* clearly out of reach for USB 1.1 like for FTDI Fifo or RS versions 
(2232 or 4232 OTOH).
* Perfect for Fast Ethernet (100M).
You just need an external Phy and our module which takes care of 
everything. We deliver a simple API on the PC side (source code) but 
you can write your own (simple sockets programming).
Demonstrators are available in many FPGA technologies and commercial 
boards.
If you have a budget and need a quick (integration takes usually less 
than one day) and efficient solution, contact us: info at alse-fr not 
calm.  :-)

Bert

On Sun, 19 Jul 2009 18:39:46 +0200, Bert_Paris <do_not_spam_@me> wrote:

>Gints :
>> hey guys,
>> I have an FPGA capturing binarizing an image and want to connect it to
>> a PC for further analysis etc. What do you think would be the best
>> protocol to use? The data itself is about 12.8 Mbits/second so was
>> leaning toward 100Mbps ethernet implemented on the FPGA. Is this
>> possible (plausible) without a soft processor, ie: just streaming the
>> images straight from the FPGA RAM? Any links to relevant readings
>> would be greatly appreciated so I could learn.
>
>Hi,
>
>We do have developed a module doing just this (streaming data both ways 
>through Ethernet). No processor, no SW stack, no external memory, no 
>MAC, no SGDMA, no RTOS... all is included in our very compact IP, 
>including the PC side SW.
>Note that it is affordable but it's NOT free.
>
>12.8 Mbits is :
>* clearly out of reach for USB 1.1 like for FTDI Fifo or RS versions 
>(2232 or 4232 OTOH).


FYI I've just been playing with the FT2232H for outputting from the PC to an FPGA, and this will
sustain 20MBytes/second one-way.
This is in parallel sync mode - the async modes are constrained by the async bus timing. 

>
> FYI I've just been playing with the FT2232H for outputting from the PC to an FPGA, and this will
> sustain 20MBytes/second one-way.
> This is in parallel sync mode - the async modes are constrained by the async bus timing.

That does sound very useful. Unfortunately I'm working on a dev board
that has an RJ45 port and a PHY, so I am just writing a very simple
UDP packet sender to test it all out. Bit of a hack way, but this is
just for testing the FPGA image processing, the final board will have
a PCI bridge to a processor, so a UDP approach should suffice for now

Mike Harrison :
> On Sun, 19 Jul 2009 18:39:46 +0200, Bert_Paris <do_not_spam_@me> wrote:
>> 12.8 Mbits is :
>> * clearly out of reach for USB 1.1 like for FTDI Fifo or RS versions 
>> (2232 or 4232 OTOH).
>
> FYI I've just been playing with the FT2232H for outputting from the PC to an 
> FPGA, and this will sustain 20MBytes/second one-way.
> This is in parallel sync mode - the async modes are constrained by the async 
> bus timing. 

Thanks Mike,

I missed the "H" at the end.

The "old" FT2232 is USB1.1 so limited to ~1Mbyte/s, and I haven't use 
the USB2.0 "H" version yet.
But now we are much more focused on Ethernet (especially Gigabit which 
is much faster & easier than USB2.0), so it may not happen soon.

Bert