I am currently working on a design using the v4fx20. My current design consists of bram memory at 0xffff0000 to 0xffffffff and DDR at 0x00000000 to 0x03ffffff. I can read and write from the bram memory, but whenever I either read or write from anywhere within the DDR memory space, my entire memory space (0x00000000 - 0xffffffff) becomes unusable. For example: XMD% mrd 0xffffff00 16 FFFFFF00: 00000000 FFFFFF04: 00000000 FFFFFF08: 00000000 FFFFFF0C: 00000000 FFFFFF10: 00000000 FFFFFF14: 00000000 FFFFFF18: 00000000 FFFFFF1C: 00000000 FFFFFF20: 00000000 FFFFFF24: 00000000 FFFFFF28: 00000000 FFFFFF2C: 00000000 FFFFFF30: 00000000 FFFFFF34: 00000000 FFFFFF38: 00000000 FFFFFF3C: 00000000 XMD% mwr 0xffffff00 0x12345678 XMD% mrd 0xffffff00 16 FFFFFF00: 12345678 FFFFFF04: 00000000 FFFFFF08: 00000000 FFFFFF0C: 00000000 FFFFFF10: 00000000 FFFFFF14: 00000000 FFFFFF18: 00000000 FFFFFF1C: 00000000 FFFFFF20: 00000000 FFFFFF24: 00000000 FFFFFF28: 00000000 FFFFFF2C: 00000000 FFFFFF30: 00000000 FFFFFF34: 00000000 FFFFFF38: 00000000 FFFFFF3C: 00000000 XMD% mrd 0x00000000 16 0: FFFFFFF8 4: FFFFFFF8 8: FFFFFFF8 C: FFFFFFF8 10: FFFFFFF8 14: FFFFFFF8 18: FFFFFFF8 1C: FFFFFFF8 20: FFFFFFF8 24: FFFFFFF8 28: FFFFFFF8 2C: FFFFFFF8 30: FFFFFFF8 34: FFFFFFF8 38: FFFFFFF8 3C: FFFFFFF8 XMD% mrd 0xffffff00 16 FFFFFF00: FFFF0958 FFFFFF04: FFFF0958 FFFFFF08: FFFF0958 FFFFFF0C: FFFF0958 FFFFFF10: FFFF0958 FFFFFF14: FFFF0958 FFFFFF18: FFFF0958 FFFFFF1C: FFFF0958 FFFFFF20: FFFF0958 FFFFFF24: FFFF0958 FFFFFF28: FFFF0958 FFFFFF2C: FFFF0958 FFFFFF30: FFFF0958 FFFFFF34: FFFF0958 FFFFFF38: FFFF0958 FFFFFF3C: FFFF0958 To me this sounds like a timing issue, but I believe I have everything constrained that needs to be constrained. It could also be a initialization issue but I'm not sure. Has anyone run into such an issue?
mpmc kills plb bus on v4fx20
Started by ●July 23, 2009
Reply by ●July 27, 20092009-07-27
"bishopg" <bishopg12@gmail.com> wrote in message news:557b39ef-b190-43db-8ad7-a460aa4e685d@c1g2000yqi.googlegroups.com...>I am currently working on a design using the v4fx20. My current > design consists of bram memory at 0xffff0000 to 0xffffffff and DDR at > 0x00000000 to 0x03ffffff. I can read and write from the bram memory, > but whenever I either read or write from anywhere within the DDR > memory space, my entire memory space (0x00000000 - 0xffffffff) becomes > unusable.Which MPMC version? How is the BRAM connected? Can you read/write your DDRAM successfully if you don't touch the BRAM? /Mikhail
Reply by ●July 27, 20092009-07-27
On Jul 24, 12:21=A0am, bishopg <bishop...@gmail.com> wrote:> I am currently working on a design using the v4fx20. =A0My current > design consists of bram memory at 0xffff0000 to 0xffffffff and DDR at > 0x00000000 to 0x03ffffff. =A0I can read and write from the bram memory, > but whenever I either read or write from anywhere within the DDR > memory space, my entire memory space (0x00000000 - 0xffffffff) becomes > unusable. =A0For example: > > XMD% mrd 0xffffff00 16 > FFFFFF00: 00000000 > FFFFFF04: 00000000 > FFFFFF08: 00000000 > FFFFFF0C: 00000000 > FFFFFF10: 00000000 > FFFFFF14: 00000000 > FFFFFF18: 00000000 > FFFFFF1C: 00000000 > FFFFFF20: 00000000 > FFFFFF24: 00000000 > FFFFFF28: 00000000 > FFFFFF2C: 00000000 > FFFFFF30: 00000000 > FFFFFF34: 00000000 > FFFFFF38: 00000000 > FFFFFF3C: 00000000 > > XMD% mwr 0xffffff00 0x12345678 > XMD% mrd 0xffffff00 16 > FFFFFF00: 12345678 > FFFFFF04: 00000000 > FFFFFF08: 00000000 > FFFFFF0C: 00000000 > FFFFFF10: 00000000 > FFFFFF14: 00000000 > FFFFFF18: 00000000 > FFFFFF1C: 00000000 > FFFFFF20: 00000000 > FFFFFF24: 00000000 > FFFFFF28: 00000000 > FFFFFF2C: 00000000 > FFFFFF30: 00000000 > FFFFFF34: 00000000 > FFFFFF38: 00000000 > FFFFFF3C: 00000000 > > XMD% mrd 0x00000000 16 > 0: FFFFFFF8 > 4: FFFFFFF8 > 8: FFFFFFF8 > C: FFFFFFF8 > 10: FFFFFFF8 > 14: FFFFFFF8 > 18: FFFFFFF8 > 1C: FFFFFFF8 > 20: FFFFFFF8 > 24: FFFFFFF8 > 28: FFFFFFF8 > 2C: FFFFFFF8 > 30: FFFFFFF8 > 34: FFFFFFF8 > 38: FFFFFFF8 > 3C: FFFFFFF8 > > XMD% mrd 0xffffff00 16 > FFFFFF00: FFFF0958 > FFFFFF04: FFFF0958 > FFFFFF08: FFFF0958 > FFFFFF0C: FFFF0958 > FFFFFF10: FFFF0958 > FFFFFF14: FFFF0958 > FFFFFF18: FFFF0958 > FFFFFF1C: FFFF0958 > FFFFFF20: FFFF0958 > FFFFFF24: FFFF0958 > FFFFFF28: FFFF0958 > FFFFFF2C: FFFF0958 > FFFFFF30: FFFF0958 > FFFFFF34: FFFF0958 > FFFFFF38: FFFF0958 > FFFFFF3C: FFFF0958 > > To me this sounds like a timing issue, but I believe I have everything > constrained that needs to be constrained. =A0It could also be a > initialization issue but I'm not sure. =A0Has anyone run into such an > issue?MPMC memory is not working, it will lock up the bus on first access to it its a known "feature" Antti
Reply by ●July 30, 20092009-07-30
On Jul 27, 5:10=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> On Jul 24, 12:21=A0am, bishopg <bishop...@gmail.com> wrote: > > > > > I am currently working on a design using the v4fx20. =A0My current > > design consists of bram memory at 0xffff0000 to 0xffffffff and DDR at > > 0x00000000 to 0x03ffffff. =A0I can read and write from the bram memory, > > but whenever I either read or write from anywhere within the DDR > > memory space, my entire memory space (0x00000000 - 0xffffffff) becomes > > unusable. =A0For example: > > > XMD% mrd 0xffffff00 16 > > FFFFFF00: 00000000 > > FFFFFF04: 00000000 > > FFFFFF08: 00000000 > > FFFFFF0C: 00000000 > > FFFFFF10: 00000000 > > FFFFFF14: 00000000 > > FFFFFF18: 00000000 > > FFFFFF1C: 00000000 > > FFFFFF20: 00000000 > > FFFFFF24: 00000000 > > FFFFFF28: 00000000 > > FFFFFF2C: 00000000 > > FFFFFF30: 00000000 > > FFFFFF34: 00000000 > > FFFFFF38: 00000000 > > FFFFFF3C: 00000000 > > > XMD% mwr 0xffffff00 0x12345678 > > XMD% mrd 0xffffff00 16 > > FFFFFF00: 12345678 > > FFFFFF04: 00000000 > > FFFFFF08: 00000000 > > FFFFFF0C: 00000000 > > FFFFFF10: 00000000 > > FFFFFF14: 00000000 > > FFFFFF18: 00000000 > > FFFFFF1C: 00000000 > > FFFFFF20: 00000000 > > FFFFFF24: 00000000 > > FFFFFF28: 00000000 > > FFFFFF2C: 00000000 > > FFFFFF30: 00000000 > > FFFFFF34: 00000000 > > FFFFFF38: 00000000 > > FFFFFF3C: 00000000 > > > XMD% mrd 0x00000000 16 > > 0: FFFFFFF8 > > 4: FFFFFFF8 > > 8: FFFFFFF8 > > C: FFFFFFF8 > > 10: FFFFFFF8 > > 14: FFFFFFF8 > > 18: FFFFFFF8 > > 1C: FFFFFFF8 > > 20: FFFFFFF8 > > 24: FFFFFFF8 > > 28: FFFFFFF8 > > 2C: FFFFFFF8 > > 30: FFFFFFF8 > > 34: FFFFFFF8 > > 38: FFFFFFF8 > > 3C: FFFFFFF8 > > > XMD% mrd 0xffffff00 16 > > FFFFFF00: FFFF0958 > > FFFFFF04: FFFF0958 > > FFFFFF08: FFFF0958 > > FFFFFF0C: FFFF0958 > > FFFFFF10: FFFF0958 > > FFFFFF14: FFFF0958 > > FFFFFF18: FFFF0958 > > FFFFFF1C: FFFF0958 > > FFFFFF20: FFFF0958 > > FFFFFF24: FFFF0958 > > FFFFFF28: FFFF0958 > > FFFFFF2C: FFFF0958 > > FFFFFF30: FFFF0958 > > FFFFFF34: FFFF0958 > > FFFFFF38: FFFF0958 > > FFFFFF3C: FFFF0958 > > > To me this sounds like a timing issue, but I believe I have everything > > constrained that needs to be constrained. =A0It could also be a > > initialization issue but I'm not sure. =A0Has anyone run into such an > > issue? > > MPMC memory is not working, it will lock up the bus on first access to > it > its a known > > "feature" > > AnttiJust figured that out. The InitDone signal was not high. Thanks, -George
