I've read about daisy chaining fpgas with Platform flash, but is daisy chaining fpgas possible with SPI flash? The documents at Xilinx seems to give only examples of single fpga configuration with SPI flash.
Daisychaining fpga with SPI flash?
Started by ●July 28, 2009
Reply by ●July 28, 20092009-07-28
On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote:> I've read about daisy chaining fpgas with Platform flash, but is daisy > chaining fpgas possible with SPI flash? > The documents at Xilinx seems to give only examples of single fpga > configuration with SPI flash.no, you cant use multiply SPI flash in chained mode (you may configure more than one FPGA from one SPI flash) well, some newer FPGA's include multi SPI support, * Spartan-6 * Lattice-SC * Achronix Speedster all support multiply SPI flash in __parallel__ wiring (maybe some others too, i do not know all ) Antti
Reply by ●July 28, 20092009-07-28
On Jul 28, 11:33=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > I've read about daisy chaining fpgas with Platform flash, but is daisy > > chaining fpgas possible with SPI flash? > > The documents at Xilinx seems to give only examples of single fpga > > configuration with SPI flash. > > no, you cant use multiply SPI flash in chained mode > (you may configure more than one FPGA from one SPI flash) > > well, some newer FPGA's include multi SPI support, > > * Spartan-6 > * Lattice-SC > * Achronix Speedster > > all support multiply SPI flash in __parallel__ wiring > (maybe some others too, i do not know all ) > > AnttiActually, I was thinking of configuring multiple FPGAs from one SPI flash, but I don't see any examples in the Spartan6 configuration document. They give only the Platform flash example, which use pins like INIT_B and PROG_B instead of MOSI in SPI. Is the connection similar to the slave serial mode one using Platform flash, and do you know of any examples?
Reply by ●July 28, 20092009-07-28
On Jul 28, 11:47=A0pm, Ben <leowy...@gmail.com> wrote:> On Jul 28, 11:33=A0pm, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > > I've read about daisy chaining fpgas with Platform flash, but is dais=y> > > chaining fpgas possible with SPI flash? > > > The documents at Xilinx seems to give only examples of single fpga > > > configuration with SPI flash. > > > no, you cant use multiply SPI flash in chained mode > > (you may configure more than one FPGA from one SPI flash) > > > well, some newer FPGA's include multi SPI support, > > > * Spartan-6 > > * Lattice-SC > > * Achronix Speedster > > > all support multiply SPI flash in __parallel__ wiring > > (maybe some others too, i do not know all ) > > > Antti > > Actually, I was thinking of configuring multiple FPGAs from one SPI > flash, but I don't see any examples in the Spartan6 configuration > document. > They give only the Platform flash example, which use pins like INIT_B > and PROG_B instead of MOSI in SPI. > Is the connection similar to the slave serial mode one using Platform > flash, and do you know of any examples?Sorry, I mean master serial mode.
Reply by ●July 28, 20092009-07-28
On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > I've read about daisy chaining fpgas with Platform flash, but is daisy > > chaining fpgas possible with SPI flash? > > The documents at Xilinx seems to give only examples of single fpga > > configuration with SPI flash. > > no, you cant use multiply SPI flash in chained mode > (you may configure more than one FPGA from one SPI flash) > > well, some newer FPGA's include multi SPI support, > > * Spartan-6 > * Lattice-SC > * Achronix Speedster > > all support multiply SPI flash in __parallel__ wiring > (maybe some others too, i do not know all ) > > AnttiI'm not sure that was what he was asking. If you have a single SPI flash big enough to hold all the bitstreams you can daisy chain the FPGA's (not the flash chips). One FPGA is in SPI master mode and the others in serial slave mode. Should be shown in the configuration UG.
Reply by ●July 28, 20092009-07-28
On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote:> On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > > I've read about daisy chaining fpgas with Platform flash, but is dais=y> > > chaining fpgas possible with SPI flash? > > > The documents at Xilinx seems to give only examples of single fpga > > > configuration with SPI flash. > > > no, you cant use multiply SPI flash in chained mode > > (you may configure more than one FPGA from one SPI flash) > > > well, some newer FPGA's include multi SPI support, > > > * Spartan-6 > > * Lattice-SC > > * Achronix Speedster > > > all support multiply SPI flash in __parallel__ wiring > > (maybe some others too, i do not know all ) > > > Antti > > I'm not sure that was what he was asking. =A0If you have a single > SPI flash big enough to hold all the bitstreams you can daisy > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master > mode and the others in serial slave mode. =A0Should be shown in the > configuration UG.Yes, I see this line "Another alternative is to use SPI mode for the first device. The daisy-chain data is still sent out through DOUT in SPI mode." Well, this is in the Serial Daisy Chain section and they use a Xilinx Platform Flash PROM.
Reply by ●July 28, 20092009-07-28
On Jul 28, 7:00=A0pm, Ben <leowy...@gmail.com> wrote:> On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote: > > > > > > > On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com" > > > <Antti.Luk...@googlemail.com> wrote: > > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > > > I've read about daisy chaining fpgas with Platform flash, but is da=isy> > > > chaining fpgas possible with SPI flash? > > > > The documents at Xilinx seems to give only examples of single fpga > > > > configuration with SPI flash. > > > > no, you cant use multiply SPI flash in chained mode > > > (you may configure more than one FPGA from one SPI flash) > > > > well, some newer FPGA's include multi SPI support, > > > > * Spartan-6 > > > * Lattice-SC > > > * Achronix Speedster > > > > all support multiply SPI flash in __parallel__ wiring > > > (maybe some others too, i do not know all ) > > > > Antti > > > I'm not sure that was what he was asking. =A0If you have a single > > SPI flash big enough to hold all the bitstreams you can daisy > > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master > > mode and the others in serial slave mode. =A0Should be shown in the > > configuration UG. > > Yes, I see this line "Another alternative is to use SPI mode for the > first device. The daisy-chain data is still sent out through DOUT in > SPI mode." > Well, this is in the Serial Daisy Chain section and they use a Xilinx > Platform Flash PROM.- Hide quoted text - > > - Show quoted text -Xilinx FPGA configuration controller has special function to BYPASS config data so you can stream it from the first device and use for any purpose you need (as config another FPGA as example) it is ir-relevant if the configuration comes from platform flash or spi flash or, you can use another approuch what i used with lattice FPGA as soon as FIRST FPGA is configured, it ROUTES the spi flash out to some downstream FPGA config interface and starts generating SPI clock, this "user config controller" is very small and doesnt take much resources Antti
Reply by ●July 28, 20092009-07-28
On Jul 28, 12:24=A0pm, "Antti.Luk...@googlemail.com" <Antti.Luk...@googlemail.com> wrote:> On Jul 28, 7:00=A0pm, Ben <leowy...@gmail.com> wrote: > > > > > On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote: > > > > On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com" > > > > <Antti.Luk...@googlemail.com> wrote: > > > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > > > > I've read about daisy chaining fpgas with Platform flash, but is =daisy> > > > > chaining fpgas possible with SPI flash? > > > > > The documents at Xilinx seems to give only examples of single fpg=a> > > > > configuration with SPI flash. > > > > > no, you cant use multiply SPI flash in chained mode > > > > (you may configure more than one FPGA from one SPI flash) > > > > > well, some newer FPGA's include multi SPI support, > > > > > * Spartan-6 > > > > * Lattice-SC > > > > * Achronix Speedster > > > > > all support multiply SPI flash in __parallel__ wiring > > > > (maybe some others too, i do not know all ) > > > > > Antti > > > > I'm not sure that was what he was asking. =A0If you have a single > > > SPI flash big enough to hold all the bitstreams you can daisy > > > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI master > > > mode and the others in serial slave mode. =A0Should be shown in the > > > configuration UG. > > > Yes, I see this line "Another alternative is to use SPI mode for the > > first device. The daisy-chain data is still sent out through DOUT in > > SPI mode." > > Well, this is in the Serial Daisy Chain section and they use a Xilinx > > Platform Flash PROM.- Hide quoted text - > > > - Show quoted text - > > Xilinx FPGA configuration controller has special function to BYPASS > config data > so you can stream it from the first device and use for any purpose you > need > (as config another FPGA as example) > > it is ir-relevant if the configuration comes from platform flash or > spi flash > > or, you can use another approuch what i used with lattice FPGA > as soon as FIRST FPGA is configured, it ROUTES the spi flash > out to some downstream FPGA config interface and starts generating > SPI clock, this "user config controller" is very small and doesnt take > much resources > > AnttiActually at least for ECP2, SPI config of multiple parts is easy with Lattice. The first FPGA is in SPI master mode and the subsequent FPGA's are in serial slave mode. First FPGA CCLK is both SPI clock and downstream CCLK for serial config. The tricky part with lattice is figuring out how to merge the bitstreams into the single SPI PROM (you need the "Universal File Writer" for this). Regards, Gabor
Reply by ●July 30, 20092009-07-30
On Jul 28, 10:18=A0am, Ben <leowy...@gmail.com> wrote:> I've read about daisy chaining fpgas with Platform flash, but is daisy > chaining fpgas possible with SPI flash? > The documents at Xilinx seems to give only examples of single fpga > configuration with SPI flash.Yes Daisy Chaining using SPI flash is possible go thru the 3E datasheet configuration option. Only take care that FPGA should not be stepping 0.
Reply by ●July 30, 20092009-07-30
On Jul 28, 9:44=A0pm, gabor <ga...@alacron.com> wrote:> On Jul 28, 12:24=A0pm, "Antti.Luk...@googlemail.com" > > > > > > <Antti.Luk...@googlemail.com> wrote: > > On Jul 28, 7:00=A0pm, Ben <leowy...@gmail.com> wrote: > > > > On Jul 28, 11:49=A0pm, gabor <ga...@alacron.com> wrote: > > > > > On Jul 28, 11:33=A0am, "Antti.Luk...@googlemail.com" > > > > > <Antti.Luk...@googlemail.com> wrote: > > > > > On Jul 28, 6:18=A0pm, Ben <leowy...@gmail.com> wrote: > > > > > > > I've read about daisy chaining fpgas with Platform flash, but i=s daisy> > > > > > chaining fpgas possible with SPI flash? > > > > > > The documents at Xilinx seems to give only examples of single f=pga> > > > > > configuration with SPI flash. > > > > > > no, you cant use multiply SPI flash in chained mode > > > > > (you may configure more than one FPGA from one SPI flash) > > > > > > well, some newer FPGA's include multi SPI support, > > > > > > * Spartan-6 > > > > > * Lattice-SC > > > > > * Achronix Speedster > > > > > > all support multiply SPI flash in __parallel__ wiring > > > > > (maybe some others too, i do not know all ) > > > > > > Antti > > > > > I'm not sure that was what he was asking. =A0If you have a single > > > > SPI flash big enough to hold all the bitstreams you can daisy > > > > chain the FPGA's (not the flash chips). =A0One FPGA is in SPI maste=r> > > > mode and the others in serial slave mode. =A0Should be shown in the > > > > configuration UG. > > > > Yes, I see this line "Another alternative is to use SPI mode for the > > > first device. The daisy-chain data is still sent out through DOUT in > > > SPI mode." > > > Well, this is in the Serial Daisy Chain section and they use a Xilinx > > > Platform Flash PROM.- Hide quoted text - > > > > - Show quoted text - > > > Xilinx FPGA configuration controller has special function to BYPASS > > config data > > so you can stream it from the first device and use for any purpose you > > need > > (as config another FPGA as example) > > > it is ir-relevant if the configuration comes from platform flash or > > spi flash > > > or, you can use another approuch what i used with lattice FPGA > > as soon as FIRST FPGA is configured, it ROUTES the spi flash > > out to some downstream FPGA config interface and starts generating > > SPI clock, this "user config controller" is very small and doesnt take > > much resources > > > Antti > > Actually at least for ECP2, SPI config of multiple parts is easy > with Lattice. =A0The first FPGA is in SPI master mode and the > subsequent FPGA's are in serial slave mode. =A0First FPGA CCLK > is both =A0SPI clock and downstream CCLK for serial config. =A0The > tricky part with lattice is figuring out how to merge the > bitstreams into the single SPI PROM (you need the "Universal > File Writer" for this). > > Regards, > Gabor- Hide quoted text - > > - Show quoted text -well, in my case the device downstream was Virtex-4 :) i think i used own tools to merge the bits Antti
