Xilinx 3E design programs fine with 500E but fails with 250E

Hi All,



We have solved this problem to a functional degree. Thanks to all for
your help. Of 56 production boards, we were able to accurately figure
out our device short falls and produce a work around solution. Some
common facts we now know about the XIlinx 250E and 500E FPGA's.



1. The problem was not associated with purchasing the device from a
non-authorised vendor or device stepping

2. The Xilinx Spartan 500E works as advertised

3. The Xilinx Spartan 250E does not work as advertised (the supplied
SPI flash programming core with ISE 10 and later is precariously
flawed)

4. Using the supplied SPI core with 250E's results in corrupt code
being written to flash causing excess (950mA+) current to be consumed
by VCCint (1V2) and the device failing to execute downloads. We dont
know what is consuming the excess current, but speculate the cause to
be from high speed boot retries of the corrupt code. As we have no
information regarding this core, we can only speculate on what our CRO
and analyser tell us.

5. Behaviour is 100% reliably repeatable.

6. All 250E boards perform correctly and pass function and performance
tests when used with tools other than Xilinx Impact and their SPI
programming core



For those stuck with the 250E and a serial SPI flash, the only
solution to program the attached SPI flash is to use Picoblaze, or
program the SPI device independently.





steve

On Aug 17, 2:32=A0am, Steve <srk...@gmail.com> wrote:

> 4. Using the supplied SPI core with 250E's results in corrupt code
> being written to flash causing excess (950mA+) current to be consumed
> by VCCint (1V2) and the device failing to execute downloads. We dont
> know what is consuming the excess current, but speculate the cause to
> be from high speed boot retries of the corrupt code.

Interesting... I had a single example of an 250E turn itself into a
space heater a few weeks back while working on code for loading it
from an embedded processor.  It had previously worked flawlessly, as
did the replacement.  Perhaps there are certain invalid bit streams
that will introduce enough internal "shorts" to kill it?

On Aug 4, 6:32=A0am, Steve <srk...@gmail.com> wrote:
> Hi Brian,
>
> Thanks for the solid response. Ill try the things you suggest to see
> if that resolves the problem, but I do have a few initial comments on
> some of these suggestions;
>
> > =A0The recommendation to select JTAG mode during indirect
> > SPI programming can be found in the newer Xilinx SPI
> > programming application notes [Ref 1].
>
> --> Thats somewhat dissapointing, as i have an existing design in
> production based on their "Designs can migrate between
> the XC3S250E and XC3S500E without further consideration." statement
> found on page 189 of their DS312 datasheet (who knows if its current,
> or true - does it matter?)
>
>
>
> > > sorta defeats having a bootable FPGA.
>
> > =A0Set it to JTAG when you connect the JTAG cable to program
> > the SPI flash with Impact, set it back when you are done...
>
> Hard to do with 0402 components, but ill bolt it on an see what
> happends.
>
>
>
> > =A0Adding a mode select jumper block hardly reduces the
> > functionality of a board, particularly when this mode
> > jumper is often needed to use the JTAG port without
> > experiencing the sort of problems that you are seeing.
>
> I think it does. For upgrades, plugging up to the JTAG port and
> downloading is a lot easier than including instructions for jumpers,
> especially when the product is closed to the world. DS312, it also
> states JTAG always gets priority over other methods, well, up until
> now. A jumper is a bug fix for this device, for xilinx. Again, may
> have to do it, but if I have to spin the board again, its just as easy
> for me to put another vendor device on there.
>
>
>
> > =A0If you want the mode selection to be automatic, the 2mm
> > 14 pin JTAG header pinout can be used to provide a JTAG
> > cable detect [Ref 2].
>
> --> I dont wish to be tied to just xilinx programmers. Native JTAG
> interface is what we are using. JTAG has too many pins as it is.
>
>
>
> > > The 500E version works fine without needing to do this.
>
> > =A0These PROM/JTAG boot conflicts can vary from part to part,
> > and between mask steppings of the same device.
>
> Ive noticed with xilinx, the same part varies as well - going with an
> xilinx ES part is suicide. However, since it was spelt out in DS312
> its ok to swap a 250E with a 500E with only code changes, I sorta
> thought that meant I could swap between a 250E and a 500E with only
> code changes.
>
> steve

Hi Steve,

i almost always used own JTAG-SPI bypass soft cores and own PC host
software for SPI flash programming
(before the feature was added to impact)

as I see the impact solution is still a problem. eh it would be so
much better if xilinx would supply source
code of the spi indirect cores... but they do not :(

Antti

> Interesting... I had a single example of an 250E turn itself into a
> space heater a few weeks back while working on code for loading it
> from an embedded processor. =A0It had previously worked flawlessly, as
> did the replacement. =A0Perhaps there are certain invalid bit streams
> that will introduce enough internal "shorts" to kill it?

Im not suprised. I feel only xilinx could achieve a hardware failure
thru code.

Ive designed with a lot of xilinx devices, and use a lot of devices
with work. They have been great. But its not like that anymore.It all
began with their idiot "inputs only" on banks, then quadrant "global"
clocks, then weird power allocations.  All their devices have short
falls now. We have put our spartan 6 products on hold for a while, but
are moving ahead with arria and Cyclone III's. Not a good sign. But
devices not working as advertised is the worst. After this last
horrible ordeal i feel i have changed camps.

Hi Antii,

Yep, i used too program direct as welll. But with the ease of using a
bridge to a standard interfcae such as SPI or BPI, i dont think I ever
want to go back to that method. Its just so easy to provide a new
level of support to your customers without have pages of inxtructions
or esoteric programming equipment. Xilinx wont fix the bug. If the bug
wasnt that bad, they would have already. The 250E is toast.



> Hi Steve,
>
> i almost always used own JTAG-SPI bypass soft cores and own PC host
> software for SPI flash programming
> (before the feature was added to impact)
>
> as I see the impact solution is still a problem. eh it would be so
> much better if xilinx would supply source
> code of the spi indirect cores... but they do not :(
>
> Antti- Hide quoted text -
>
> - Show quoted text -

On Aug 20, 10:55=A0am, Steve <srk...@gmail.com> wrote:
> Hi Antii,
>
> Yep, i used too program direct as welll. But with the ease of using a
> bridge to a standard interfcae such as SPI or BPI, i dont think I ever
> want to go back to that method. Its just so easy to provide a new
> level of support to your customers without have pages of inxtructions
> or esoteric programming equipment. Xilinx wont fix the bug. If the bug
> wasnt that bad, they would have already. The 250E is toast.
>
>
>
> > Hi Steve,
>
> > i almost always used own JTAG-SPI bypass soft cores and own PC host
> > software for SPI flash programming
> > (before the feature was added to impact)
>
> > as I see the impact solution is still a problem. eh it would be so
> > much better if xilinx would supply source
> > code of the spi indirect cores... but they do not :(
>
> > Antti- Hide quoted text -
>
> > - Show quoted text -- Hide quoted text -
>
> - Show quoted text -

I did NOT program SPI-direct :)

I programed SPI indirect using my own JTAG IP cores and pc side
software

Antti

Hi Antii,

Wow, I missed that bit - ive been so used to info not being what I
wanted to read, that I totally over looked the fact you had written
your own!
Dangling that carrot in front of me is too much, so

Would it be ok if I could have a copy??


Thanks,
Steve

> > Hi Antii,
>
> > Yep, i used too program direct as welll. But with the ease of using a
> > bridge to a standard interfcae such as SPI or BPI, i dont think I ever
> > want to go back to that method. Its just so easy to provide a new
> > level of support to your customers without have pages of inxtructions
> > or esoteric programming equipment. Xilinx wont fix the bug. If the bug
> > wasnt that bad, they would have already. The 250E is toast.
>
> > > Hi Steve,
>
> > > i almost always used own JTAG-SPI bypass soft cores and own PC host
> > > software for SPI flash programming
> > > (before the feature was added to impact)
>
> > > as I see the impact solution is still a problem. eh it would be so
> > > much better if xilinx would supply source
> > > code of the spi indirect cores... but they do not :(
>
> > > Antti- Hide quoted text -
>
> > > - Show quoted text -- Hide quoted text -
>
> > - Show quoted text -
>
> I did NOT program SPI-direct :)
>
> I programed SPI indirect using my own JTAG IP cores and pc side
> software
>
> Antti- Hide quoted text -
>
> - Show quoted text -

> 
> I did NOT program SPI-direct :)
> 
> I programed SPI indirect using my own JTAG IP cores and pc side
> software
> 

 From the time it takes impact to "indirectly" program a 500E even when 
it works it appears that they use JTAG to toggle the FPGA's pins so that 
it communicates with the EEPROM. At the same time Xilinx has an app note 
with a Picoblaze doing the flashing that works just fine but requires 
another serial channel. I wonder what stops them from creating a "UART" 
via the JTAG "user" instruction and use that. So I ended up creating a 
core that read the bits from a memory card and programs the flash in a 
few seconds.

P.S. I'm the other person on Steve's project. His "we" was not royal.


-Alex.

Alex Freed <alex_news@mirrow.com> writes:

> requires another serial channel. I wonder what stops them from
> creating a "UART" via the JTAG "user" instruction and use that. So I

I've been using the JTAG user module to program various attached
devices for many years. Should not be a problem, but of course the
vendors would probably like you to use their device specific IP.

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On Aug 21, 4:08=A0am, Alex Freed <alex_n...@mirrow.com> wrote:
> > I did NOT program SPI-direct :)
>
> > I programed SPI indirect using my own JTAG IP cores and pc side
> > software
>
> =A0From the time it takes impact to "indirectly" program a 500E even when
> it works it appears that they use JTAG to toggle the FPGA's pins so that
> it communicates with the EEPROM. At the same time Xilinx has an app note
> with a Picoblaze doing the flashing that works just fine but requires
> another serial channel. I wonder what stops them from creating a "UART"
> via the JTAG "user" instruction and use that. So I ended up creating a
> core that read the bits from a memory card and programs the flash in a
> few seconds.
>
> P.S. I'm the other person on Steve's project. His "we" was not royal.
>
> -Alex.

the BSCAN can almost directly be bypassed to IO for SPI indirect
i used hower a very small core for this

hm, if i recall i had intermediate sync protocol what i called SSP
(sync serial protocol) what is essentially spi without select :)
so i had BSCAN-SSP and SSP-SPI modules

the beaty of that is that it is really simple to convert SPI flash
programming data to say SVF and play back that SVF
to the FPGA JTAG and the spi chips gets accessed

i did not use svf/jam (but own software), however using svf/jam would
be easy too, then you can use vendor tools to access the jtag
interface (impact, quartus programmer, whatever)

funny.. I am just now thinking about putting live into that project
http://groups.google.com/group/antti-brain/files?hl=3Den

U2TOOL jpeg ist current development photo of the hardware gadget
it is already working as USB Blaster and I was able to use Actel
SVF converted to jam, and Altera commandline jam player to
program an ProAsic3 :)
I wonted to test with Stratix board, but i thas the +- in the 9V jack
reversed :(

I had for some years another nice application, FPGA freqeuncy meter
it used LPT based JTAG cable and measured frequency (without the
need of any known clocks connected to FPGA), with usb cables
that isnt possible, well with U2TOOL it will be again.. so it makes
fun
to develop it.

i can dig up my JTAG-SPI ip cores.. the approuch was rather nice
(specially because of easy svf/jam programming)

Antti