Driving Multiple FPGAs and Fanout (Cyclone III)

Hi,

I have a design that will comprise of 11 FPGA boards: 10 slaves and 1
master and each board is having one cyclone III FPGA. The communication
between master and slaves is via a simple SRAM protocol (with addr, data,
WR/RD and CS). All boards will be interconnected together on a backplane
board, with about 1 inch apart.

According to the electrical specifications, the input leakage current of
each pin is only 10uA. Therefore, in the case of LVTTL with 4mA drive
strength, theoretically one master could drive up to 400 slaves? Is this
too good to believe? Also, overshoot voltage could be a problem if signals
are not terminated. Altera recommended 33R series resistor on each line.
Does anyone have similar experience on this?

I also would like to know what is the real benefit of using LVCMOS apart
from LVTTL.

Any recommendation is much appreciated.

On Aug 5, 9:18=A0am, "snowball67" <wti...@singnet.com.sg> wrote:
> Hi,
>
> I have a design that will comprise of 11 FPGA boards: 10 slaves and 1
> master and each board is having one cyclone III FPGA. The communication
> between master and slaves is via a simple SRAM protocol (with addr, data,
> WR/RD and CS). All boards will be interconnected together on a backplane
> board, with about 1 inch apart.
>
> According to the electrical specifications, the input leakage current of
> each pin is only 10uA. Therefore, in the case of LVTTL with 4mA drive
> strength, theoretically one master could drive up to 400 slaves? Is this
> too good to believe? Also, overshoot voltage could be a problem if signal=
s
> are not terminated. Altera recommended 33R series resistor on each line.
> Does anyone have similar experience on this?
>
> I also would like to know what is the real benefit of using LVCMOS apart
> from LVTTL.
>
> Any recommendation is much appreciated.

Since the days of bipolar TTL logic, the DC loading has never been
the limiting factor for fanout.  With CMOS, your load is essentially
a capacitor.  400 10pF loads becomes 4 nF.  Think of the rise and
fall times your LVTTL or LVCMOS signal can achieve under these
conditions!

Series termination is a bad idea when driving a backplane.  And
driving the clocks, or asynchronous command signals if there
is no clock, requires incident wave switching.  Unless you want
to run your "simple" SRAM interface at a fairly low speed, I
would suggest re-thinking your interconnect.  Perhaps with
the same number of wires, but arranged as point-to-point
connections in a loop, you could run at many times the data
rate while easily achieving good signal integrity.

Just my 2 cents,
Gabor

"snowball67" <wtiong@singnet.com.sg> wrote in message 
news:Vr2dndTtLoMMG-TXnZ2dnUVZ_jGdnZ2d@giganews.com...
> Hi,
>
> I have a design that will comprise of 11 FPGA boards: 10 slaves and 1
> master and each board is having one cyclone III FPGA. The communication
> between master and slaves is via a simple SRAM protocol (with addr, data,
> WR/RD and CS). All boards will be interconnected together on a backplane
> board, with about 1 inch apart.
>
> According to the electrical specifications, the input leakage current of
> each pin is only 10uA. Therefore, in the case of LVTTL with 4mA drive
> strength, theoretically one master could drive up to 400 slaves? Is this
> too good to believe? Also, overshoot voltage could be a problem if signals
> are not terminated. Altera recommended 33R series resistor on each line.
> Does anyone have similar experience on this?
>
> I also would like to know what is the real benefit of using LVCMOS apart
> from LVTTL.
>
> Any recommendation is much appreciated.
>
>

There is more to consider than just the input leakage current of each 
receiver as it only indicates what is possible for static signals. If all 
your signals never change state then, yes, each driver can drive 400 
receivers. Of course, this isn't the reality of your situation.

The input capacitance of each receiver, the rise/fall time of the driver, 
the characteristic impedance of all the traces, and the termination scheme 
used will determine whether the setup and hold times for data lines are met, 
whether the edge requirements for the clock lines are met, and whether the 
undershoot/overshoot specs for all signals are met.

Unless your rise/fall times are very long with respect to all the trace 
propagation times, you'll need to get someone else involved that can guide 
you through these "signal integrity" issues. You can, to some degree, 
control the rise/fall times of FPGA output drivers. However, slower edge 
rates mean lower data rates (must always meet setup and hold reqs on data 
lines and dv/dt reqs on clock lines).

The main advantage of LVCMOS over LVTTL is that LVCMOS input switching 
thresholds are farther from their associated outputs' nominal signal level. 
This allows for more "noise" (signal distortion) at the receiver while still 
meeting input logic level requirements.

Bob
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