Spartan-6 Boards - Your Wish List

DJ Delorie wrote:

> Or better, have it ship pre-programmed to be a standalone web browser
> - softcpu; drivers for vga, keyboard, mouse, ethernet; mini-OS,
> browser.  Plug everything in and go, then learn how to do it yourself.

This would be a lifetime project for most students. I think starting with
low-level gates is a good idea. First with real ones, like 7400 DIL. Then
maybe with schematics editor and FPGAs, because it is much easier to build
with the mouse than with wires, but the result, testing in real hardware,
is the same. Finally some simple programs in VHDL. There are always some
students who want to implement a web browser after this :-)

-- 
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

M.Randelzhofer <techseller@gmx.de> wrote:


 >A functional copy of an old homecomputer like Apple ][ or C64 could motivate 
 >students mostly to learn logic design, i think.

I don't think so. This will work only with students older than 40,
because fresh new students around 20 have never seen such computer and
have no feelings for it. 

Olaf

What would be a widely useful feature is the inclusion of a FTDI FT2232H USB2.0 Hi-speed interface -
this is a really easy way to get 20mbytes/sec bandwidth from a PC with minimal work at either end. 

Depending on space, one of : 
1) 2232H chip on board with standard or mini-USB connector
2) pair of Headers for the FT2232H mini module ( 2x26 pin 0.1" headers)
3) Single 2-row header for just the CN2 header of the module. If you look at the pinouts you'll see
that by putting a standard 0.1" jumper link between pins 1 and 3 of their CN1 header, you can do
everything else to get the high-speed sync parallel interface or one of the two async parallel
interfaces with just CN2 - you just need to link the VCCIO and 3V3 pins on this header and put the
grounds in the right place  
This could also be used as a general-purpose IO header for other applications. 

Unless you're really pushed for space, the cost/usefulness tradeoff of option 3 has to be a
no-brainer....

 

We are already looking at the FT2232H and related parts principally
for performance. It's not as elegant a solution as the FT232R that we
have in existing designs and also several of the launch candidates. It
would be nice if FTDI did a high performance version of the FT232R but
meanwhile we will look at the FT2232H. In the idea world a FTDI style
part, with all the easy use stuff, and with the performance of the
Cypress familiy of parts would be the ideal as a manufacturer.

We do have some plans for add on modules using the FTDI parts as well.
Also some upgrades of our existing Cypress based USB2 module are
coming.

John Adair
Enterpoint Ltd.

On 12 Aug, 09:57, Mike Harrison <m...@whitewing.co.uk> wrote:
> What would be a widely useful feature is the inclusion of a FTDI FT2232H =
USB2.0 Hi-speed interface -
> this is a really easy way to get 20mbytes/sec bandwidth from a PC with mi=
nimal work at either end.
>
> Depending on space, one of :
> 1) 2232H chip on board with standard or mini-USB connector
> 2) pair of Headers for the FT2232H mini module ( 2x26 pin 0.1" headers)
> 3) Single 2-row header for just the CN2 header of the module. If you look=
 at the pinouts you'll see
> that by putting a standard 0.1" jumper link between pins 1 and 3 of their=
 CN1 header, you can do
> everything else to get the high-speed sync parallel interface or one of t=
he two async parallel
> interfaces with just CN2 - you just need to link the VCCIO and 3V3 pins o=
n this header and put the
> grounds in the right place =A0
> This could also be used as a general-purpose IO header for other applicat=
ions.
>
> Unless you're really pushed for space, the cost/usefulness tradeoff of op=
tion 3 has to be a
> no-brainer....

John Adair <g1@enterpoint.co.uk> wrote:
> We are already looking at the FT2232H and related parts principally
> for performance. It's not as elegant a solution as the FT232R that we
> have in existing designs and also several of the launch candidates. It
> would be nice if FTDI did a high performance version of the FT232R but
> meanwhile we will look at the FT2232H. In the idea world a FTDI style
> part, with all the easy use stuff, and with the performance of the
> Cypress familiy of parts would be the ideal as a manufacturer.

In what area the FT232R is mnore elegant.

With very few external muxes with the FT2232H you can
- serve the JTAG Chain and provide a high speed links to the PC
  readable as COMx or ttyUSBx
- or provide two high speed links to the PC
  readable as COMx or ttyUSBx
- or provide one 20 MB+/s link.

No need to generate UART data...

-- 
Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

Institut fuer Kernphysik  Schlossgartenstrasse 9  64289 Darmstadt
--------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

In article <1se3s9w5bxodj.1jbhy6iv9zya3$.dlg@40tude.net>,
 Frank Buss <fb@frank-buss.de> writes:
|> 
|> This would be a lifetime project for most students. I think starting with
|> low-level gates is a good idea. First with real ones, like 7400 DIL. Then
|> maybe with schematics editor and FPGAs

I like to object here.

At our university we're teaching VHDL to undergrads and grads; the former
have no previous knowledge of hardware design. Therefore, they start with 
simple tasks like blinkenlights and stuff, but then quickly move on to 
design a VGA picture generator, and finally create their own pong clone, 
altering the original gameplay by further ideas ranging from auto-player, 
multi-ball, reverse-gravity etc. (A presentation of this course was recently 
given at CDNlive2009 in Munich.)

In the grad course, the students design and *manually* implement (i.e. not
using EDK but doing completely custom designs) their own multicore CPUs
incl. VGA output, with a demo program to be implemented which e.g. is 
a distributed Mandelbrot set computation.

Both courses take 4 hours per week and run for 14 weeks, i.e. during the
teaching time of a semester.

Letting them implement low-level gates doesn't really achieve much in
terms of HDL design; and teaching them the old way of constructing
schematics based on a prefabricated set of standard chips also doesn't
do much good regarding the use of *high-level* hardware-design languages.

Rainer

The FT232R is nice because it does not need external eeprom, crystal
and the trming caps and resistors. It is all in the very small tiny
QFN package.  All these bits are external to the FT2232 unless I
missed something and hence takes X10-20 the pcb area which is still
small but noticeable. For all this it is also very cheap even in low
numbers.

If you don't need performance the FT232R is pretty much in a class of
it's own although I think there may be some compeditor parts now
trying to catch up and do the same.

John Adair
Enterpoint Ltd.

On 12 Aug, 11:25, Uwe Bonnes <b...@elektron.ikp.physik.tu-
darmstadt.de> wrote:
> John Adair <g...@enterpoint.co.uk> wrote:
> > We are already looking at the FT2232H and related parts principally
> > for performance. It's not as elegant a solution as the FT232R that we
> > have in existing designs and also several of the launch candidates. It
> > would be nice if FTDI did a high performance version of the FT232R but
> > meanwhile we will look at the FT2232H. In the idea world a FTDI style
> > part, with all the easy use stuff, and with the performance of the
> > Cypress familiy of parts would be the ideal as a manufacturer.
>
> In what area the FT232R is mnore elegant.
>
> With very few external muxes with the FT2232H you can
> - serve the JTAG Chain and provide a high speed links to the PC
> =A0 readable as COMx or ttyUSBx
> - or provide two high speed links to the PC
> =A0 readable as COMx or ttyUSBx
> - or provide one 20 MB+/s link.
>
> No need to generate UART data...
>
> --
> Uwe Bonnes =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0b...@elektron.ikp.physik.tu-dar=
mstadt.de
>
> Institut fuer Kernphysik =A0Schlossgartenstrasse 9 =A064289 Darmstadt
> --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------

Wearing one of my other hats as an an employeer, one of the things
that we don't get are graduates with an understanding, of what they
are actually getting, when they synthesise a FPGA design. Engineers of
my generation that actually worked with 74 series logic etc.and
retrained in FPGAs generally can visualise logic much easier and can
cope with low level interpretation of designs when there is an issue.
We do have more than occassional call for that skill when we are
fixing difficult FPGA designs. However I don't think doing major
student projects in schematic is called for but some basic
understanding, of small end low level stuff, would be useful .

John Adair
Enterpoint Ltd.

On 12 Aug, 13:15, buc...@atbode100.lrr.in.tum.de (Rainer Buchty)
wrote:
> In article <1se3s9w5bxodj.1jbhy6iv9zya3$....@40tude.net>,
> =A0Frank Buss <f...@frank-buss.de> writes:
> |>
> |> This would be a lifetime project for most students. I think starting w=
ith
> |> low-level gates is a good idea. First with real ones, like 7400 DIL. T=
hen
> |> maybe with schematics editor and FPGAs
>
> I like to object here.
>
> At our university we're teaching VHDL to undergrads and grads; the former
> have no previous knowledge of hardware design. Therefore, they start with
> simple tasks like blinkenlights and stuff, but then quickly move on to
> design a VGA picture generator, and finally create their own pong clone,
> altering the original gameplay by further ideas ranging from auto-player,
> multi-ball, reverse-gravity etc. (A presentation of this course was recen=
tly
> given at CDNlive2009 in Munich.)
>
> In the grad course, the students design and *manually* implement (i.e. no=
t
> using EDK but doing completely custom designs) their own multicore CPUs
> incl. VGA output, with a demo program to be implemented which e.g. is
> a distributed Mandelbrot set computation.
>
> Both courses take 4 hours per week and run for 14 weeks, i.e. during the
> teaching time of a semester.
>
> Letting them implement low-level gates doesn't really achieve much in
> terms of HDL design; and teaching them the old way of constructing
> schematics based on a prefabricated set of standard chips also doesn't
> do much good regarding the use of *high-level* hardware-design languages.
>
> Rainer

On Aug 12, 7:15=A0am, buc...@atbode100.lrr.in.tum.de (Rainer Buchty)
wrote:
>
> Letting them implement low-level gates doesn't really achieve much in
> terms of HDL design; and teaching them the old way of constructing
> schematics based on a prefabricated set of standard chips also doesn't
> do much good regarding the use of *high-level* hardware-design languages.
>
> Rainer

I agree. It has been 25 years since I was in school, but today's
students need to learn boolean logic, not TTL logic. Learning with HDL
not only gets them headed in the right direction (don't use schematics
for logic design), but also helps avoid some of the pitfalls of
"netlist" coding styles in HDL (this process is gates, that process is
registers, etc.)  Most of today's students have some background in SW,
and while HW design is not SW design, the similarities WRT the process
are substantial. SW techniques like scope control (not talking about
tweaking knobs on a lab instrument here), information hiding,
development for maintenance and support, testing, etc. all apply to
HDL design as well, not to mention the benefits of learning HDL
testbench techniques. And to make all of this "real", they can
implement it on an FPGA development board. (there, I got it back on
the OP's subject).

Andy

In article <e0cebfb5-1f3a-416f-b981-f6d6f2f6847a@s15g2000yqs.googlegroups.com>,
 John Adair <g1@enterpoint.co.uk> writes:
|> Wearing one of my other hats as an an employeer, one of the things
|> that we don't get are graduates with an understanding, of what they
|> are actually getting, when they synthesise a FPGA design.
|> Engineers of my generation that actually worked with 74 series logic etc.and
|> retrained in FPGAs generally can visualise logic much easier and can
|> cope with low level interpretation of designs when there is an issue.

I'm fully with you there, but I would think that forcing people towards
space/area-constraint design would achieve similar understanding.

Personally, I believe that the major problem these days (be it hardware
or software design) is that people have somewhat "unlimited" resources
at their hands. The average computer's emory size has increased 3 orders 
of magnitude during the last 25 years, likewise the logic capacity of
FPGAs is now at a size which was unbelievable even 10 years ago.

|> We do have more than occassional call for that skill when we are
|> fixing difficult FPGA designs. However I don't think doing major
|> student projects in schematic is called for but some basic
|> understanding, of small end low level stuff, would be useful .

Agreed, but probably not that low-level as Frank suggested, i.e. trying
to transform 74xx into VHDL models. Especially as the understanding
required for those kind of jobs definitely includes understanding of
the architecture and how things may be mapped onto it.

Regarding the mentioned undergrad course, one goal was getting an idea on
what it takes to create certain machine setups in hardware; in this very
case it was meant for preservation, i.e. designing full-system emulators
where the original software would still run on. The final lab project
therefore was about a compatible re-creation of an existing arcade machine 
within an FPGA. Here, the focus was more put on understanding "alien" code,
extending it, and and making it work within an own design rather than 
writing anything own stuff as required in the preceding tasks.

If you're interested, the poster gives a quick overview:
        http://itec.uka.de/~buchty/pub/2009-cdnlive-poster.pdf

with the extended abstract being this:
	http://itec.uka.de/~buchty/pub/2009-cdnlive.pdf

Rainer