algorithm implementation in IC

Hi,all
   I'm not a FPGA engineer or IC designer.
In fact, I'm a DSP engineer. So I have little
knowledge about FPGA and IC design. I am
wandering the way that a algorithm is implemented
in IC. In IC desgin, the first step is algorithm
design and C model implementation. Do algorithm
engineers need to know FPGA implementation details
In this step? If they have no idea about FPGA
implementation, the algorithm may not be implemented
efficiently in FPGA. When algorithm engineers know FPGA
well they choose the efficent methods which can
minimize area and power consumption. If FPGA engineers
know little about algorithms, they can't make trade off
between algorithm complexity and implementation efficiency.
There is a gap between algorithm design and FPGA implementation.
In IC industry, how is this problem solved?

Best Regards
Jogging

> There is a gap between algorithm design and FPGA implementation.
> In IC industry, how is this problem solved?

You're not much of an "algorithm engineer" if you don't know how
something will be implemented.

Jon

On 11 Aug., 11:01, jogging <joggings...@gmail.com> wrote:
>  In IC desgin, the first step is algorithm
> design and C model implementation.
I always wondered why anyone would want to model the algorithms in
C nowadays. There are so many nice modern languages around with
object orientation, etc.
Prototyping should be much quicker and less error prone with any of
these
compared to C.

> Do algorithm
> engineers need to know FPGA implementation details
> In this step?

I think it is sufficient to have some information on the cost of
various
operations, like the number and size of RAMs, Multipliers, FIFOs etc.
And some informations on the relativ speed of these operations.


Kolja Sulimma

jogging <joggingsong@gmail.com> wrote:

<   I'm not a FPGA engineer or IC designer.
< In fact, I'm a DSP engineer. So I have little
< knowledge about FPGA and IC design. I am
< wandering the way that a algorithm is implemented
< in IC. In IC desgin, the first step is algorithm
< design and C model implementation. Do algorithm
< engineers need to know FPGA implementation details
< In this step? 

I don't believe that they necessarily need FPGA implementation
details, but they do need to think in terms of logic design.

Some people believe that FPGA implementations are software
because they can be done in high-level languages like verilog,
or even C.  I disagree.  You have to be able to think in terms
of digital logic.  If you can do that, for example as TTL gates,
then I believe that you can do algorithm design for FPGAs.
It IS significantly different from DSP (software) design.

Once the algorithm has been designed, such as in the form 
of a systolic array, then someone else can do the actual
coding and optimizing for the specific FPGA.

-- glen

On Tue, 11 Aug 2009 06:24:40 -0700 (PDT), Kolja
<ksulimma@googlemail.com> wrote:

>On 11 Aug., 11:01, jogging <joggings...@gmail.com> wrote:
>>  In IC desgin, the first step is algorithm
>> design and C model implementation.
>I always wondered why anyone would want to model the algorithms in
>C nowadays. There are so many nice modern languages around with
>object orientation, etc.
>Prototyping should be much quicker and less error prone with any of
>these compared to C.

Maybe it's because there are a lot of behavioral synthesis products
for C which actually work (or at least much more promising these days
(albeit very expensive)).
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

On Tue, 11 Aug 2009 02:01:39 -0700 (PDT), jogging
<joggingsong@gmail.com> wrote:

>Hi,all
>   I'm not a FPGA engineer or IC designer.
>In fact, I'm a DSP engineer. So I have little
>knowledge about FPGA and IC design. I am
>wandering the way that a algorithm is implemented
>in IC. In IC desgin, the first step is algorithm
>design and C model implementation. Do algorithm
>engineers need to know FPGA implementation details
>In this step? If they have no idea about FPGA
>implementation, the algorithm may not be implemented
>efficiently in FPGA. When algorithm engineers know FPGA
>well they choose the efficent methods which can
>minimize area and power consumption. If FPGA engineers
>know little about algorithms, they can't make trade off
>between algorithm complexity and implementation efficiency.
>There is a gap between algorithm design and FPGA implementation.
>In IC industry, how is this problem solved?

While converting an algorithm implemented in C (with an underlying OS)
there are 3 main issues: 1) partitioning (which parts of the
implementation goes lower to hardware implementation and which parts
stay at processor level) 2) Scheduling 3) dynamic range (or floating
point vs fixed point).
Assuming partitioning is done early & correctly, the main issues of
ASIC/FPGA implementation are scheduling and dynamic range both of
which relate to hardware resource use. Scheduling requires decisions
on how much logic is needed in "one cycle" and is an optimization for
latency, hardware resource use and timing. Dynamic range is mostly for
hardware resource and timing (FP is big & slow).
So when doing algorithm development you need to pay attention to how
complicated the logic is in one cycle of a loop(s) and whether you are
using floating point numbers or whether you can implement all your
logic with integers. There are several tools which convert C to
Verilog RTL these days and you can see the results relatively quickly
to make changes to original C design. But nothing beats experience of
someone who codes in C and finally ports to Verilog to be able to tell
how easy the conversion will be.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Muzaffer Kal <kal@dspia.com> wrote:
 
< Maybe it's because there are a lot of behavioral synthesis products
< for C which actually work (or at least much more promising these days
< (albeit very expensive)).

What do you mean by 'work'?

If there is software that can convert a serial dynamic programming
implementation into a systolic array in an FPGA I will be really really
surprised.

To me, the advantage to using C would be the ability to
use existing code, but serial code ports very poorly to hardware.
In addition, it allows people to believe that they can do logic
design without thinking about logic.  

Actually, I don't even code (for the most part) behavioral verilog.
(FFs can only be done in behavioral form, but I put them in a 
separate module, anyway.)

-- glen

On Tue, 11 Aug 2009 19:43:29 +0000 (UTC), glen herrmannsfeldt
<gah@ugcs.caltech.edu> wrote:

>Muzaffer Kal <kal@dspia.com> wrote:
> 
>< Maybe it's because there are a lot of behavioral synthesis products
>< for C which actually work (or at least much more promising these days
>< (albeit very expensive)).
>
>What do you mean by 'work'?
>
Check out the following products and decide for yourself:
Mentor Catapult C
Celoxica Handel C
Forte CSynthesizer
Synfora PICO

>If there is software that can convert a serial dynamic programming
>implementation into a systolic array in an FPGA I will be really really
>surprised.
>
Get ready to be surprised (to some degree).

>To me, the advantage to using C would be the ability to
>use existing code, but serial code ports very poorly to hardware.
>In addition, it allows people to believe that they can do logic
>design without thinking about logic.  

Nothing wrong with that as long as it increases productivity and
generates acceptable products. People had the same complaints about C
vs assembly, schematics vs Verilog/VHDL and even probably grunts vs
speech.
--
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

"Muzaffer Kal" <kal@dspia.com> wrote in message 
news:3ij385lab9krukgklp7lkbm3l9olbac40b@4ax.com...
> On Tue, 11 Aug 2009 19:43:29 +0000 (UTC), glen herrmannsfeldt
> <gah@ugcs.caltech.edu> wrote:
>
>>Muzaffer Kal <kal@dspia.com> wrote:
>>
>>< Maybe it's because there are a lot of behavioral synthesis products
>>< for C which actually work (or at least much more promising these days
>>< (albeit very expensive)).
>>
>>What do you mean by 'work'?
>>
> Check out the following products and decide for yourself:
> Mentor Catapult C
> Celoxica Handel C
> Forte CSynthesizer
> Synfora PICO

Some lunchtime reading:

http://www.deepchip.com/gadfly/gad071409.html

I agree with Muzaffer and IMHO behavioural (untimed) synthesis is definitely the 
way forward. Currently with all these tools (at least CatapultC) you still need 
to be a hardware engineer to drive them but with each new release the 
swingometer is slowly moving towards the dark (software) side.

Hans
www.ht-lab.com

Thanks, Kolja

On Aug 11, 9:24=A0pm, Kolja <ksuli...@googlemail.com> wrote:
> On 11 Aug., 11:01, jogging <joggings...@gmail.com> wrote:> =A0In IC desgi=
n, the first step is algorithm
> > design and C model implementation.
>
> I always wondered why anyone would want to model the algorithms in
> C nowadays. There are so many nice modern languages around with
> object orientation, etc.
> Prototyping should be much quicker and less error prone with any of
> these
> compared to C.
I am not a IC design engineer, so not familiar with practice in IC
industry.
I'm only curious the way how the gap between algorithm design and
FPGA implementation is solved.
From wikipedia, it says
ESL design: This step creates the user functional specification. The
user may use a variety of languages and tools to create this
description. Examples include a C/C++ model, SystemC, SystemVerilog
Transaction Level Models, Simulink and MATLAB.

Do you mean MATLAB is used to develop prototype?
What are the most popular languages to develop prototype?

>
> > Do algorithm
> > engineers need to know FPGA implementation details
> > In this step?
>
> I think it is sufficient to have some information on the cost of
> various
> operations, like the number and size of RAMs, Multipliers, FIFOs etc.
> And some informations on the relativ speed of these operations.
>
> Kolja Sulimma

Best Regards
Jogging