Multiple Interrupt handling in XPS 8.2i

Iam using XPS 8.2i.I have built a custom peripheral and attached it
to
MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two
interrupts.These interrupts pins are input to the interrupt
controller
INTC (1.00 c).
Initially both interrupts are disabled.Then only high priority
interrupt is enabled.
What my objective is that when a high priority interrupt occurs:in
its
ISR it should disabled itself and enabled the other interrupt on
interrupt controller.
But actually what is happening that when high priority interrupt is
occurred it goes into its ISR and it doesnot disable itself.the other
interrupt is enabled and the microblaze is stuck in handling both the
interrupts.
Any help in this regard is welcomed!

You must make sure to acknowledge the interrupt source (your custom
core), and then the interrupt controller after each interrupt event
(as well as the CPU-specific interrupt handling).  Otherwise, the
active interrupt source will immediately trigger another interrupt as
soon as you exit your ISR.

-Jason

On Aug 20, 1:01=A0am, moon <moon3...@gmail.com> wrote:
> Iam using XPS 8.2i.I have built a custom peripheral and attached it
> to
> MicroBlaze (v 5.0) via OPB bus.My peripheral generates the two
> interrupts.These interrupts pins are input to the interrupt
> controller
> INTC (1.00 c).
> Initially both interrupts are disabled.Then only high priority
> interrupt is enabled.
> What my objective is that when a high priority interrupt occurs:in
> its
> ISR it should disabled itself and enabled the other interrupt on
> interrupt controller.
> But actually what is happening that when high priority interrupt is
> occurred it goes into its ISR and it doesnot disable itself.the other
> interrupt is enabled and the microblaze is stuck in handling both the
> interrupts.
> Any help in this regard is welcomed!