The custom board that I am working on has a SDRAM and parallel NOR- FLASH, and they share the same address and data I/0 pins in the FPGA. SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller. Since they use different memory controllers I need to implement some logic in order to multiplex signals that come from the controllers to the external pins. Data buses are bidirectional which can only be connected to the external pins. Is there any work (logic code) has been done to share the same IO pins to access SDRAM and FLASH ? Any suggestions will be very helpful to me in order to implement logic to access both sdram and flash using a single bit file.
sharing sdram and parallel nor flash address/data bus using xilinx edk
Started by ●August 28, 2009
Reply by ●August 29, 20092009-08-29
On Aug 28, 11:40=A0pm, john1529 <mon...@gmail.com> wrote:> The custom =A0board that I am working on has a SDRAM and parallel NOR- > FLASH, and they share the same address and data I/0 pins in the FPGA. > SDRAM uses mpmc controller and FLASH uses xps_mch_emc controller. > Since they use different memory controllers I need to implement some > logic in order to multiplex signals that come from the controllers to > the external pins. Data buses are bidirectional which can only be > connected to the external pins. Is there any work (logic code) has > been done to share the same IO pins to access SDRAM and FLASH ? Any > suggestions will be very helpful to me in order to implement logic to > access both sdram and flash using a single bit file.inout buses can be split to _I _O _T and recombined as needed in EDK but i am pretty sure you CAN NOT use SDRAM/mpmc and NOR/mch_emc when address/data io pins are shared mpmc assumes it can always start sdram cycle when needed, there is no wait for ready signal for arbiter and the mpmc requests may still be pending when nor controller wants to acces the bus, so it would be conflicts.. BUMMER! Antti