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Bidirectional Bus

Started by nobody ●September 7, 2009
After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
data and fpga_cclk into the FPGA the done pin goes high. The problem I
am having is the bidirectional does not release and allow the FPGA to
drive the data bus to CPLD and then finally into an external 8 LED
bank. I am fairly confident that the FPGA is loaded correctly with the
bin file, by accident I reprogrammed the CPLD releasing the bus the
FPGA, having been programmed, drove the bidirectional data bus and the
lit the 8 LED bank appropriately. Any help on this issues would be
apprciated, thank you. CODE:


----------------------------------------------------------------------------------
-- Company: 		Electronic Realization L.L.C.
-- Engineer: 		Cy Drollinger
-- Create Date:   	10:44:37 07/08/2009
-- Design Name: 	USB/FPGA Spartan3E Develpoement
-- Module Name:   	CPLD - Behavioral
-- Project Name:
-- Target Devices: 	XC2C64A VQ100
-- Tool versions:
-- Description:
-- Dependencies:
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---- Uncomment the following library declaration if instantiating
---- any Xilinx primitives in this code.
library UNISIM;
use UNISIM.VComponents.all;

entity CPLD is
    Port ( 													--CPLD LOCATIONS
			--Master clock oscillator 50 MHz CTS - CB3
		mclk : in  STD_LOGIC;								--pin 22
		mclk_ce : out  STD_LOGIC;							--pin 70 Logic

			--Xilinx Spartan 3E VQ100 mode and variant
		Variant : out  STD_LOGIC_VECTOR (2 downto 0);			--pin 34, 33, 30
		Mode : out  STD_LOGIC_VECTOR (2 downto 0);				--pin 42, 39, 36

			--Xilinx Spartan 3E VQ100
		FPGA_MOSI : out  STD_LOGIC;							--pin 90 this is also CSI_B
		FPGA_BUSY : in  STD_LOGIC;							--pin 91 if clk is less than 50 MHz
		FPGA_INITB : in  STD_LOGIC;							--pin 92
		FPGA_CSO_B : inout STD_LOGIC;						--pin 94
		FPGA_cclk	: out	STD_LOGIC:='0';					--pin 27
		FPGA_done : inout  STD_LOGIC;						--pin 28
		FPGA_prog_B: inout STD_LOGIC;						--pin 99
		FPGA_HSWAP: out STD_LOGIC;						--pin 24
		FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0);			--pin 89 81 79 78 77
41 40 35

			--Numonyx M25P16
		SPI_flash_HOLD : out  STD_LOGIC;						--pin 76 SPI '1'
		SPI_flash_W : out  STD_LOGIC;							--pin 97	SPI '1'

			--FTDI FT245RL USB to parallel output
		usb_pwren : inout  STD_LOGIC;							--pin 43
		usb_wr : in  STD_LOGIC;								--pin 49
		usb_rd : inout STD_LOGIC;								--pin 50
		data : inout  STD_LOGIC_VECTOR (7 downto 0);				--pin 56 53 55 61 52
60 58 64
		usb_tx : in  STD_LOGIC;								--pin 67
		usb_rx : in  STD_LOGIC;								--pin 68 when low data ready
		usb_rst : inout  STD_LOGIC;							--pin 14

			--User I/O
		LEDs : out  STD_LOGIC_VECTOR (8 downto 1);				--pin 1-4 and 6-9
		SW : inout  STD_LOGIC_VECTOR (2 downto 0));				--pin 71, 72, 74 need
to be

end CPLD;

architecture Behavioral of CPLD is

		--FPGA Configuration

signal SW_0_hi			:std_logic;								--CPLD is in a all I/O pullups
signal SW_1_hi			:std_logic;								--CPLD is in a all I/O pullups
signal SW_2_hi			:std_logic;								--CPLD is in a all I/O pullups
Signal fpga_timing		: integer range 0 to 256	:=0;
Signal bidir_bus			:std_logic_vector (7 downto 0);
Signal bidir_reg			:std_logic_vector (7 downto 0);
Signal done			:std_logic;
		--FTDI USB chip overhead

signal usb_dry 				:std_logic;								--signal is a synchronized
signal previous_usb_dry 		:std_logic;								--signal is the value of
signal previous 				:std_logic;
Signal usb_timing		        : integer range 0 to 256	:=4;

BEGIN

--------------------------------------------------------------------------------------------------------------------------------------
-- Author		: Cy Drollinger
-- Date			: 7-16-09
-- Description	: synchronizing asynchronous inpoputs usb data ready
line(sub_rx),  SW(0), SW(1), and SW(2)
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
					--HARDWARE SYSTEM ON PCB					--TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Synchronize_inputs: process(mclk)
begin
    if rising_edge(mclk) then
      if usb_rx = '0' then												-- RXF# 	is an active
usb_dry <= '1';
		else
usb_dry <= '0';
		end if;
previous <= usb_dry;
previous_usb_dry <= previous;
		if SW(0) = '1' then
SW_0_hi <= '1';
		else
SW_0_hi <= '0';
		end if;
		if SW(1) = '1' then
SW_1_hi <= '1';
		else
SW_1_hi <= '0';
	 end if;
	 if SW(2) <= '1' then
SW_2_hi <= '1';
		else
SW_2_hi <= '0';
	 end if;
	end if;
end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author		: Cy Drollinger
-- Date			: 7-16-09
-- Description	: Upon SW(1) going low the FGPA_prog_b pulses (ONE
SHOT) high for two mclks.
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
					--HARDWARE SYSTEM ON PCB					--TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Pulse_Prog_B: process (mclk)											--
begin
	if rising_edge(mclk) then
		if SW_1_hi = '0' and FPGA_timing < 22 then
FPGA_timing <= FPGA_timing + 1;
			if fpga_timing > 0 and fpga_timing < 21 then
fpga_prog_b <= '0';
			else
fpga_prog_b <= '1';												-- fpga_prog_b held low for
			end if;
		else 	if SW_1_hi = '1' then
fpga_timing <= 0;
				end if;
		end if;
	end if;

end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author		: Cy Drollinger
-- Date			: 7-16-09
-- Description	: providing timing for usb_rd through usb_data_rdy Data
sheet DSFT245R1 pg. 12 fifo read
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
					--HARDWARE SYSTEM ON PCB					--TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Load_FPGA_Slave_Parallel: process(mclk)									--
begin
	if rising_edge(mclk) then
			if usb_dry = '1' and previous_usb_dry ='0' and fpga_initb = '1'
then
usb_timing <= 0;
			elsif usb_timing < 5 then
usb_timing <= usb_timing + 1;
			end if;
	case usb_timing is
					when 0 =>
usb_rd <='0';
					when 1 =>
usb_rd <='0';
					when 2 =>
usb_rd <='0';
					when 3 =>
usb_rd <='0';
fpga_cclk <= '1';
					when 4 =>
usb_rd <='1';
fpga_cclk <= '0';
					when others =>
		end case;
	end if;
end process;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author		: unknown
-- Date			: 9-7-09
-- Description	: LED MUX between initial programming of FPGA and data
out of FPGA
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
					--HARDWARE SYSTEM ON PCB					--TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
Bidirectional_FF:    PROCESS(mclk)
    BEGIN
    IF rising_edge(mclk) THEN 										-- Creates the flipflops
        bidir_reg <= data;
        LEDs <= not(bidir_bus);
        END IF;
    END PROCESS;


Bidirectional_Bus  PROCESS (FPGA_done, FPGA_d)          				--
Behavioral representation
        BEGIN                    											-- of tri-states.
        IF FPGA_done = '1'  THEN
            FPGA_d <= "ZZZZZZZZ";
            bidir_bus <= FPGA_d;
        ELSE
            FPGA_d <= bidir_reg;
            bidir_bus <= FPGA_d;
        END IF;
    END PROCESS;

--------------------------------------------------------------------------------------------------------------------------------------
-- Author		: Cy Drollinger
-- Date			: 6-18-09
-- Description	: Hardwiring the CPLD for the board configuration of
the usb and fpga
--------------------------------------------------------------------------------------------------------------------------------------
--SIGNAL ASSIGNMENT
					--HARDWARE SYSTEM ON PCB					--TECHNICAL COMMENTS
--------------------------------------------------------------------------------------------------------------------------------------
					--Master clock oscillator 50 MHz CTS - CB3
mclk_ce <= '1';												--enables the 50 MHz
					-- Xilinx Spartan 3E VQ100 mode and variant
Mode <= "110";												--mode Slave Parallel
					--Xilinx Spartan 3E Slave Parallel
fpga_mosi <= '0';
					--FTDI USB PARALLEL
usb_rst <= SW_0_hi;
end Behavioral;
Reply by Antt...@googlemail.com ●September 8, 20092009-09-08
On Sep 8, 4:34=A0am, nobody <cydrollin...@gmail.com> wrote:

> After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
> an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
> data and fpga_cclk into the FPGA the done pin goes high. The problem I
> am having is the bidirectional does not release and allow the FPGA to
> drive the data bus to CPLD and then finally into an external 8 LED
> bank. I am fairly confident that the FPGA is loaded correctly with the
> bin file, by accident I reprogrammed the CPLD releasing the bus the
> FPGA, having been programmed, drove the bidirectional data bus and the
> lit the 8 LED bank appropriately. Any help on this issues would be
> apprciated, thank you. CODE:
>
> -------------------------------------------------------------------------=

---------

> -- Company: =A0 =A0 =A0 =A0 =A0 =A0 Electronic Realization L.L.C.
> -- Engineer: =A0 =A0 =A0 =A0 =A0 =A0Cy Drollinger
> -- Create Date: =A0 =A0 =A0 =A0 10:44:37 07/08/2009
> -- Design Name: =A0 =A0 =A0 =A0 USB/FPGA Spartan3E Develpoement
> -- Module Name: =A0 =A0 =A0 =A0 CPLD - Behavioral
> -- Project Name:
> -- Target Devices: =A0 =A0 =A0XC2C64A VQ100
> -- Tool versions:
> -- Description:
> -- Dependencies:
> -- Revision:
> -- Revision 0.01 - File Created
> -- Additional Comments:
> -------------------------------------------------------------------------=

---------

> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> library UNISIM;
> use UNISIM.VComponents.all;
>
> entity CPLD is
> =A0 =A0 Port ( =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--C=
PLD LOCATIONS

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Master clock oscillator=

 50 MHz CTS - CB3

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk : in =A0STD_LOGIC; =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 --pin 22

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk_ce : out =A0STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --pin 70 Logic

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100=

 mode and variant

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Variant : out =A0STD_LOGIC_VECTOR (2 down=

to 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 34, 33, 30

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Mode : out =A0STD_LOGIC_VECTOR (2 downto =

0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 42, 39=
, 36

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_MOSI : out =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 90 this is also CSI_B

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_BUSY : in =A0STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0--pin 91 if clk is less than 50 MHz

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_INITB : in =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 92

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_CSO_B : inout STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 94

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_cclk =A0 =A0 =A0 : out =A0 STD_LOGIC=

:=3D'0'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 27

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_done : inout =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 --pin 28

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_prog_B: inout STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 99

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_HSWAP: out STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0--pin 24

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0=

); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 89 81 79 78 77

> 41 40 35
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Numonyx M25P16
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_HOLD : out =A0STD_LOGIC; =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0--pin 76 SPI '1'

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_W : out =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 97 =A0 =A0 =A0 =A0SPI '1'

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI FT245RL USB to par=

allel output

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_pwren : inout =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 43

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_wr : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 49

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rd : inout STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 50

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data : inout =A0STD_LOGIC_VECTOR (7 downt=

o 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 56 53 55=
 61 52

> 60 58 64
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_tx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 67

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 68 when low data ready

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rst : inout =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 14

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --User I/O
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDs : out =A0STD_LOGIC_VECTOR (8 downto =

1); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 1-4 an=
d 6-9

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SW : inout =A0STD_LOGIC_VECTOR (2 downto =

0)); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 71, 72, =
74 need

> to be
>
> end CPLD;
>
> architecture Behavioral of CPLD is
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FPGA Configuration
>
> signal SW_0_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> signal SW_1_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> signal SW_2_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> Signal fpga_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range 0 to 256 =

=A0 =A0 =A0 =A0:=3D0;

> Signal bidir_bus =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=

c_vector (7 downto 0);

> Signal bidir_reg =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=

c_vector (7 downto 0);

> Signal done =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI USB chip overhead
>
> signal usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_lo=

gic; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is a synchroni=
zed

> signal previous_usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic; =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is the value of

> signal previous =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 :std_logic;

> Signal usb_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : integer r=

ange 0 to 256 =A0 =A0 =A0 =A0:=3D4;

>
> BEGIN
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: synchronizing asynchronous inpoputs usb data ready
> line(sub_rx), =A0SW(0), SW(1), and SW(2)
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Synchronize_inputs: process(mclk)
> begin
> =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 if usb_rx =3D '0' then =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0-- RXF# =A0 =A0 =A0 =A0 is an active

> usb_dry <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> usb_dry <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> previous <=3D usb_dry;
> previous_usb_dry <=3D previous;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(0) =3D '1' then
> SW_0_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_0_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(1) =3D '1' then
> SW_1_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_1_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 =A0if SW(2) <=3D '1' then
> SW_2_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_2_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: Upon SW(1) going low the FGPA_prog_b pulses (ONE
> SHOT) high for two mclks.
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Pulse_Prog_B: process (mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--

> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW_1_hi =3D '0' and FPGA_timing < 22 t=

hen

> FPGA_timing <=3D FPGA_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if fpga_timing > 0 and fp=

ga_timing < 21 then

> fpga_prog_b <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> fpga_prog_b <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- fpga_prog_b held =
low for

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else =A0 =A0if SW_1_hi =3D '1' then
> fpga_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
>
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: providing timing for usb_rd through usb_data_rdy Data
> sheet DSFT245R1 pg. 12 fifo read
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Load_FPGA_Slave_Parallel: process(mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --

> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if usb_dry =3D '1' and pr=

evious_usb_dry =3D'0' and fpga_initb =3D '1'

> then
> usb_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif usb_timing < 5 then
> usb_timing <=3D usb_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 case usb_timing is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 0 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 1 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 2 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 3 =3D>

> usb_rd <=3D'0';
> fpga_cclk <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 4 =3D>

> usb_rd <=3D'1';
> fpga_cclk <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when others =3D>

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : unknown
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 9-7-09
> -- Description =A0: LED MUX between initial programming of FPGA and data
> out of FPGA
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Bidirectional_FF: =A0 =A0PROCESS(mclk)
> =A0 =A0 BEGIN
> =A0 =A0 IF rising_edge(mclk) THEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Creates the flipflops

> =A0 =A0 =A0 =A0 bidir_reg <=3D data;
> =A0 =A0 =A0 =A0 LEDs <=3D not(bidir_bus);
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> Bidirectional_Bus =A0PROCESS (FPGA_done, FPGA_d) =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--

> Behavioral representation
> =A0 =A0 =A0 =A0 BEGIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 -- of tri-states.

> =A0 =A0 =A0 =A0 IF FPGA_done =3D '1' =A0THEN
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D "ZZZZZZZZ";
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 ELSE
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D bidir_reg;
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 6-18-09
> -- Description =A0: Hardwiring the CPLD for the board configuration of
> the usb and fpga
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --Master clock oscillator 50 MHz CTS - CB3

> mclk_ce <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--enables the 50=
 MHz

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 -- Xilinx Spartan 3E VQ100 mode and variant

> Mode <=3D "110"; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --mode Slave Parallel

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --Xilinx Spartan 3E Slave Parallel

> fpga_mosi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --FTDI USB PARALLEL

> usb_rst <=3D SW_0_hi;
> end Behavioral;


dear nobody!

just a comment, why do you write it so complex?
just write

FPGA_d <=3D "ZZZZZZZZ" when FPGA_done =3D '1'  else bidir_bus;

outside of process of course

it will defenetly put FPGA_d pins to tristate if done is 1

Antti
Reply by nobody ●September 8, 20092009-09-08
> Antti


Thanks Antti,

Ive tried that.

Cy drollinger
Reply by Antt...@googlemail.com ●September 9, 20092009-09-09
On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:

> > Antti
>
> Thanks Antti,
>
> Ive tried that.
>
> Cy drollinger


and? problem solved or not?

Antti
Reply by nobody ●September 9, 20092009-09-09
On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:

> On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > Antti
>
> > Thanks Antti,
>
> > Ive tried that.
>
> > Cy drollinger
>
> and? problem solved or not?
>
> Antti


Antti,

No, That has the same effect as the current VDHL Bidirectional bus
attempt. The FPGA is being programmed but the bus does not release. It
releases when the CPLD is reprogrammed via JTAG, this is not an
option. I am not to familiar with driving a common trace between two
programmable chips and maybe missing something conceptually. I have
been just reading examples of bidirectional buses and have used a
couple different solutions, which are quite similar. All have the same
effect not releasing after the slave parallel programming of the FPGA
is complete. I might not be explaining the problem thoroughly. Well,
back at it. I will let you know when I get the problem solved.

Cy Drollinger
Reply by Antt...@googlemail.com ●September 9, 20092009-09-09
On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:

> On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > Antti
>
> > > Thanks Antti,
>
> > > Ive tried that.
>
> > > Cy drollinger
>
> > and? problem solved or not?
>
> > Antti
>
> Antti,
>
> No, That has the same effect as the current VDHL Bidirectional bus
> attempt. The FPGA is being programmed but the bus does not release. It
> releases when the CPLD is reprogrammed via JTAG, this is not an
> option. I am not to familiar with driving a common trace between two
> programmable chips and maybe missing something conceptually. I have
> been just reading examples of bidirectional buses and have used a
> couple different solutions, which are quite similar. All have the same
> effect not releasing after the slave parallel programming of the FPGA
> is complete. I might not be explaining the problem thoroughly. Well,
> back at it. I will let you know when I get the problem solved.
>
> Cy Drollinger


connect done to JUMPER
bus to free IO
test

the code works, so if you dont see bus released problem is somewhere
else

Antti
Reply by nobody ●September 9, 20092009-09-09
On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
<antti.luk...@googlemail.com> wrote:

> On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
>
>
> > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > <antti.luk...@googlemail.com> wrote:
> > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > Antti
>
> > > > Thanks Antti,
>
> > > > Ive tried that.
>
> > > > Cy drollinger
>
> > > and? problem solved or not?
>
> > > Antti
>
> > Antti,
>
> > No, That has the same effect as the current VDHL Bidirectional bus
> > attempt. The FPGA is being programmed but the bus does not release. It
> > releases when the CPLD is reprogrammed via JTAG, this is not an
> > option. I am not to familiar with driving a common trace between two
> > programmable chips and maybe missing something conceptually. I have
> > been just reading examples of bidirectional buses and have used a
> > couple different solutions, which are quite similar. All have the same
> > effect not releasing after the slave parallel programming of the FPGA
> > is complete. I might not be explaining the problem thoroughly. Well,
> > back at it. I will let you know when I get the problem solved.
>
> > Cy Drollinger
>
> connect done to JUMPER
> bus to free IO
> test
>
> the code works, so if you dont see bus released problem is somewhere
> else
>
> Antti


Antti,

What about the synthesis tool not actually handling the the VHDL
statement:

the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;

in the appropriate way. I asked a question about setting a pullup on a
few of the Switch pins of the CPLD and I learned that using a pullup
on one of the pin in the XC2C64A causes all pins to in a pullup state.
After talking with another individual their maybe some primitives that
need to be instantiated in order for the the high Z bus to be
implemented?
I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
100 ns, I know the FPGA can drive the LEDs through the CPLD and the
pins that programmed the FPGA, but not immediately after the CPLD
programs the FPGA. The CPLD must be reprogrammed through the JTAG
leading me to believe there is something wrong with the above VHDL
statement either in timing, something hangs, or the synthesis tool is
not performing what I think I am asking it to do, Go to a high Z state
after the FPGA is programmed.

Antti, Thank you for taking time to give solutions and time thinking
about my problem, it is appreciated.

Cy Drollinger
Reply by Antt...@googlemail.com ●September 9, 20092009-09-09
On Sep 9, 8:37=A0pm, nobody <cydrollin...@gmail.com> wrote:

> On Sep 9, 10:03=A0am, "Antti.Luk...@googlemail.com"
>
>
>
> <antti.luk...@googlemail.com> wrote:
> > On Sep 9, 6:28=A0pm, nobody <cydrollin...@gmail.com> wrote:
>
> > > On Sep 8, 10:07=A0pm, "Antti.Luk...@googlemail.com"
>
> > > <antti.luk...@googlemail.com> wrote:
> > > > On Sep 9, 1:58=A0am, nobody <cydrollin...@gmail.com> wrote:
>
> > > > > > Antti
>
> > > > > Thanks Antti,
>
> > > > > Ive tried that.
>
> > > > > Cy drollinger
>
> > > > and? problem solved or not?
>
> > > > Antti
>
> > > Antti,
>
> > > No, That has the same effect as the current VDHL Bidirectional bus
> > > attempt. The FPGA is being programmed but the bus does not release. I=

t

> > > releases when the CPLD is reprogrammed via JTAG, this is not an
> > > option. I am not to familiar with driving a common trace between two
> > > programmable chips and maybe missing something conceptually. I have
> > > been just reading examples of bidirectional buses and have used a
> > > couple different solutions, which are quite similar. All have the sam=

e

> > > effect not releasing after the slave parallel programming of the FPGA
> > > is complete. I might not be explaining the problem thoroughly. Well,
> > > back at it. I will let you know when I get the problem solved.
>
> > > Cy Drollinger
>
> > connect done to JUMPER
> > bus to free IO
> > test
>
> > the code works, so if you dont see bus released problem is somewhere
> > else
>
> > Antti
>
> Antti,
>
> What about the synthesis tool not actually handling the the VHDL
> statement:
>
> the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;
>
> in the appropriate way. I asked a question about setting a pullup on a
> few of the Switch pins of the CPLD and I learned that using a pullup
> on one of the pin in the XC2C64A causes all pins to in a pullup state.
> After talking with another individual their maybe some primitives that
> need to be instantiated in order for the the high Z bus to be
> implemented?
> I know the CPLD programs the FPGA I know the FPGA_done pin goes high,
> 100 ns, I know the FPGA can drive the LEDs through the CPLD and the
> pins that programmed the FPGA, but not immediately after the CPLD
> programs the FPGA. The CPLD must be reprogrammed through the JTAG
> leading me to believe there is something wrong with the above VHDL
> statement either in timing, something hangs, or the synthesis tool is
> not performing what I think I am asking it to do, Go to a high Z state
> after the FPGA is programmed.
>
> Antti, Thank you for taking time to give solutions and time thinking
> about my problem, it is appreciated.
>
> Cy Drollinger



the_bus <=3D "ZZZZZZZZ" when FPGA_done =3D'1' else bus_reg;

this WILL RELEASE the pins.
even Xilinx tools cant be that bad to fail on this.

if this is what you have, and FPGA_done IS 1
then bus is tristated as well

if not take a break.
it helps

if you think the synthesis tools fail, DO AS I TOLD YOU
make the "Z" on spare pins of the CPLD and check with multimeter and
finger

what you are doing is SO simple.. its hard todo it wrong...

Antti
Reply by Antt...@googlemail.com ●September 9, 20092009-09-09
On Sep 8, 4:34=A0am, nobody <cydrollin...@gmail.com> wrote:

> After programming an FPGA, XC3S250EVQ100, via Slave Parallel through
> an FTDI USB translator and a CPLD, XC2C64AVQ100, which synchronize
> data and fpga_cclk into the FPGA the done pin goes high. The problem I
> am having is the bidirectional does not release and allow the FPGA to
> drive the data bus to CPLD and then finally into an external 8 LED
> bank. I am fairly confident that the FPGA is loaded correctly with the
> bin file, by accident I reprogrammed the CPLD releasing the bus the
> FPGA, having been programmed, drove the bidirectional data bus and the
> lit the 8 LED bank appropriately. Any help on this issues would be
> apprciated, thank you. CODE:
>
> -------------------------------------------------------------------------=

---------

> -- Company: =A0 =A0 =A0 =A0 =A0 =A0 Electronic Realization L.L.C.
> -- Engineer: =A0 =A0 =A0 =A0 =A0 =A0Cy Drollinger
> -- Create Date: =A0 =A0 =A0 =A0 10:44:37 07/08/2009
> -- Design Name: =A0 =A0 =A0 =A0 USB/FPGA Spartan3E Develpoement
> -- Module Name: =A0 =A0 =A0 =A0 CPLD - Behavioral
> -- Project Name:
> -- Target Devices: =A0 =A0 =A0XC2C64A VQ100
> -- Tool versions:
> -- Description:
> -- Dependencies:
> -- Revision:
> -- Revision 0.01 - File Created
> -- Additional Comments:
> -------------------------------------------------------------------------=

---------

> library IEEE;
> use IEEE.STD_LOGIC_1164.ALL;
> use IEEE.STD_LOGIC_ARITH.ALL;
> use IEEE.STD_LOGIC_UNSIGNED.ALL;
>
> ---- Uncomment the following library declaration if instantiating
> ---- any Xilinx primitives in this code.
> library UNISIM;
> use UNISIM.VComponents.all;
>
> entity CPLD is
> =A0 =A0 Port ( =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--C=
PLD LOCATIONS

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Master clock oscillator=

 50 MHz CTS - CB3

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk : in =A0STD_LOGIC; =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 --pin 22

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 mclk_ce : out =A0STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --pin 70 Logic

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100=

 mode and variant

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Variant : out =A0STD_LOGIC_VECTOR (2 down=

to 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 34, 33, 30

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Mode : out =A0STD_LOGIC_VECTOR (2 downto =

0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 42, 39=
, 36

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Xilinx Spartan 3E VQ100
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_MOSI : out =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 90 this is also CSI_B

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_BUSY : in =A0STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0--pin 91 if clk is less than 50 MHz

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_INITB : in =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 92

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_CSO_B : inout STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 94

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_cclk =A0 =A0 =A0 : out =A0 STD_LOGIC=

:=3D'0'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 27

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_done : inout =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 --pin 28

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_prog_B: inout STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --=
pin 99

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_HSWAP: out STD_LOGIC; =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0--pin 24

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 FPGA_D: inout STD_LOGIC_VECTOR(7 downto 0=

); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 89 81 79 78 77

> 41 40 35
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --Numonyx M25P16
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_HOLD : out =A0STD_LOGIC; =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0--pin 76 SPI '1'

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SPI_flash_W : out =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 97 =A0 =A0 =A0 =A0SPI '1'

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI FT245RL USB to par=

allel output

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_pwren : inout =A0STD_LOGIC; =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 --pin 43

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_wr : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 49

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rd : inout STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 50

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 data : inout =A0STD_LOGIC_VECTOR (7 downt=

o 0); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 56 53 55=
 61 52

> 60 58 64
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_tx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 67

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rx : in =A0STD_LOGIC; =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 --pin 68 when low data ready

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 usb_rst : inout =A0STD_LOGIC; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 --pin 14

>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --User I/O
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 LEDs : out =A0STD_LOGIC_VECTOR (8 downto =

1); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--pin 1-4 an=
d 6-9

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 SW : inout =A0STD_LOGIC_VECTOR (2 downto =

0)); =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --pin 71, 72, =
74 need

> to be
>
> end CPLD;
>
> architecture Behavioral of CPLD is
>
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FPGA Configuration
>
> signal SW_0_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> signal SW_1_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> signal SW_2_hi =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logic; =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --CPLD is in a all I/O pullups

> Signal fpga_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0: integer range 0 to 256 =

=A0 =A0 =A0 =A0:=3D0;

> Signal bidir_bus =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=

c_vector (7 downto 0);

> Signal bidir_reg =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_logi=

c_vector (7 downto 0);

> Signal done =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --FTDI USB chip overhead
>
> signal usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0:std_lo=

gic; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is a synchroni=
zed

> signal previous_usb_dry =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 :std_logic; =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --signal is the value of

> signal previous =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 :std_logic;

> Signal usb_timing =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : integer r=

ange 0 to 256 =A0 =A0 =A0 =A0:=3D4;

>
> BEGIN
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: synchronizing asynchronous inpoputs usb data ready
> line(sub_rx), =A0SW(0), SW(1), and SW(2)
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Synchronize_inputs: process(mclk)
> begin
> =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 if usb_rx =3D '0' then =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0-- RXF# =A0 =A0 =A0 =A0 is an active

> usb_dry <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> usb_dry <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> previous <=3D usb_dry;
> previous_usb_dry <=3D previous;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(0) =3D '1' then
> SW_0_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_0_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW(1) =3D '1' then
> SW_1_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_1_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 =A0if SW(2) <=3D '1' then
> SW_2_hi <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> SW_2_hi <=3D '0';
> =A0 =A0 =A0 =A0 =A0end if;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: Upon SW(1) going low the FGPA_prog_b pulses (ONE
> SHOT) high for two mclks.
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Pulse_Prog_B: process (mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--

> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if SW_1_hi =3D '0' and FPGA_timing < 22 t=

hen

> FPGA_timing <=3D FPGA_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if fpga_timing > 0 and fp=

ga_timing < 21 then

> fpga_prog_b <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else
> fpga_prog_b <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0-- fpga_prog_b held =
low for

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 else =A0 =A0if SW_1_hi =3D '1' then
> fpga_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 end if;
>
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 7-16-09
> -- Description =A0: providing timing for usb_rd through usb_data_rdy Data
> sheet DSFT245R1 pg. 12 fifo read
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Load_FPGA_Slave_Parallel: process(mclk) =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 --

> begin
> =A0 =A0 =A0 =A0 if rising_edge(mclk) then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 if usb_dry =3D '1' and pr=

evious_usb_dry =3D'0' and fpga_initb =3D '1'

> then
> usb_timing <=3D 0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 elsif usb_timing < 5 then
> usb_timing <=3D usb_timing + 1;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end if;
> =A0 =A0 =A0 =A0 case usb_timing is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 0 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 1 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 2 =3D>

> usb_rd <=3D'0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 3 =3D>

> usb_rd <=3D'0';
> fpga_cclk <=3D '1';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when 4 =3D>

> usb_rd <=3D'1';
> fpga_cclk <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 when others =3D>

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 end case;
> =A0 =A0 =A0 =A0 end if;
> end process;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : unknown
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 9-7-09
> -- Description =A0: LED MUX between initial programming of FPGA and data
> out of FPGA
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> Bidirectional_FF: =A0 =A0PROCESS(mclk)
> =A0 =A0 BEGIN
> =A0 =A0 IF rising_edge(mclk) THEN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- Creates the flipflops

> =A0 =A0 =A0 =A0 bidir_reg <=3D data;
> =A0 =A0 =A0 =A0 LEDs <=3D not(bidir_bus);
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> Bidirectional_Bus =A0PROCESS (FPGA_done, FPGA_d) =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--

> Behavioral representation
> =A0 =A0 =A0 =A0 BEGIN =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 -- of tri-states.

> =A0 =A0 =A0 =A0 IF FPGA_done =3D '1' =A0THEN
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D "ZZZZZZZZ";
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 ELSE
> =A0 =A0 =A0 =A0 =A0 =A0 FPGA_d <=3D bidir_reg;
> =A0 =A0 =A0 =A0 =A0 =A0 bidir_bus <=3D FPGA_d;
> =A0 =A0 =A0 =A0 END IF;
> =A0 =A0 END PROCESS;
>
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> -- Author =A0 =A0 =A0 =A0 =A0 =A0 =A0 : Cy Drollinger
> -- Date =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 : 6-18-09
> -- Description =A0: Hardwiring the CPLD for the board configuration of
> the usb and fpga
> -------------------------------------------------------------------------=

-------------------------------------------------------------

> --SIGNAL ASSIGNMENT
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --HARDWARE SYSTEM ON PCB =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--TECHNICAL COMMENTS

> -------------------------------------------------------------------------=

-------------------------------------------------------------

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --Master clock oscillator 50 MHz CTS - CB3

> mclk_ce <=3D '1'; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=

 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0--enables the 50=
 MHz

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 -- Xilinx Spartan 3E VQ100 mode and variant

> Mode <=3D "110"; =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 --mode Slave Parallel

> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --Xilinx Spartan 3E Slave Parallel

> fpga_mosi <=3D '0';
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =

=A0 =A0 --FTDI USB PARALLEL

> usb_rst <=3D SW_0_hi;
> end Behavioral;


BTW why are you doing something like this?
to clone that
http://www.demandperipherals.com/

there is no reason todo that IMHO

Antti
PS there is no reason to connect data bus to the CPLD :)

the SPI flash can be programmed without that too..
so just DISCONNECT the data bus from the cpld
connect FT245 to FPGA directly
Reply by nobody ●September 9, 20092009-09-09
Antti,

Do not want to raise any hackles, but you are correct about the
demandperipherials knock off, perceptive. I talked with Bob Smith
about a couple of things and he basically said go away, I understand
and with no further ado I did. Here is a picture of my finished
product, http://www.mediafire.com/?sharekey=923066edf8d516eeed24a2875c7fa58ee04e75f6e8ebb871

I agree about the so simple part, However there is something
interesting in this problem I have described, I just have not found
it.

SPI works fine and is not part of the usb programming, indirect JTAG
only.

I am not sure how the FT245RL can strobe its own read line and produce
a CCLK in order to load the data into FPGA, if you are willing to
elaborate im willing to read.

I went for a swim to clear my head it works every time.

Will give your suggestions a closer look.

I have so much completed on this board from absolutely nothing to 95%
working it is a great project and will be taking this open source. I
wonder why my work is not necessary?

Antti, thanks for chatting not looking to raise any hackles, but am
glad for the help.

Cy Drollinger