ANN: Coding style guidance for FPGA memory

As promised several weeks ago, I've written up a document
and code examples - in both Verilog and VHDL - summarizing 
ways to create synthesizable memory in FPGAs.  It's not
rocket science; all the information in it is already 
available from synthesis and FPGA vendor docs.  However,
it may be helpful to have an independent summary of it 
in one place.  There's also a discussion of some possible
pitfalls that may be useful.

The PDF document, and source code examples, are available
for free download at

  http://www.doulos.com/knowhow/fpga/technotes/

We ask for registration, but if you accept the cookie you
can then get any other related downloads from our site
without re-registering.

On the same page there's also a document, written by my
colleague Alan Fitch, outlining various ways to make 
FPGA designs generic and re-usable in VHDL.

As always, suggestions for correction and improvement
of the content will be warmly welcomed.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

Hi Jonathan


Thanks for producing these very interesting documents.

Since I prefer to avoid using primitives, having a slick template for
declaring DPRAMs with the different R/W priority is a great help.  The
discussion about reuse and portability is a also very nice read !


Regards

Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
> We ask for registration,

Er, your privacy policy says you can spam us and change your policy at
any time.  Can we get something a little more user-friendly than that?

DJ Delorie wrote:
> Jonathan Bromley <jonathan.bromley@MYCOMPANY.com> writes:
>> We ask for registration,
> 
> Er, your privacy policy says you can spam us and change your policy at
> any time.  Can we get something a little more user-friendly than that?

I haven't been spammed yet.
There is a checkbox option to turn email off.

Note that tested vhdl synthesis examples that
that make use of vhdl's unfair adavantages
as well as standard libraries, are rare.

       -- Mike Treseler

On 9 Sep, 17:48, DJ Delorie <d...@delorie.com> wrote:
> Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> writes:
> > We ask for registration,
>
> Er, your privacy policy says you can spam us and change your policy at
> any time. =A0Can we get something a little more user-friendly than that?

Ah, now I remember why I have several trashable gmail and yahoo
accounts.
Is my name Colin?... sometimes it's hard to remember.

I haven't looked at Jonathan's paper yet, but for at least the
last 3 years, there have been generic memory models on OpenCores.
I believe they are available in Verilog only, but to the best of
my knowledge they can be synthesized to memories with Xilinx,
Altera, and several Std. Cell libraries. Might be worth to
take a cool  ...

Cheers,
rudi

On Sat, 12 Sep 2009 23:02:46 -0700 (PDT), luudee wrote:

>I haven't looked at Jonathan's paper yet, but for at least the
>last 3 years, there have been generic memory models on OpenCores.

Could you give a more specific pointer?  The best I could
find on the new-look OpenCores was Jamil Khatib's models,
written quite a long time ago and lacking some of the 
features that you need to work with RAMs in modern FPGAs.
I probably wasn't looking in the right place, though.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Sep 13, 11:59=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Sat, 12 Sep 2009 23:02:46 -0700 (PDT), luudee wrote:
> >I haven't looked at Jonathan's paper yet, but for at least the
> >last 3 years, there have been generic memory models on OpenCores.
>
> Could you give a more specific pointer? =A0The best I could
> find on the new-look OpenCores was Jamil Khatib's models,
> written quite a long time ago and lacking some of the
> features that you need to work with RAMs in modern FPGAs.
> I probably wasn't looking in the right place, though.
> --
> Jonathan Bromley, Consultant
>
> DOULOS - Developing Design Know-how
> VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services
>
> Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
> jonathan.brom...@MYCOMPANY.comhttp://www.MYCOMPANY.com
>
> The contents of this message may contain personal views which
> are not the views of Doulos Ltd., unless specifically stated.

the place is right

just that the models are of no good in many cases

Antti

Mike Treseler wrote:

> Note that tested vhdl synthesis examples that
> that make use of vhdl's unfair adavantages
                                   advantages

> as well as standard libraries, are rare.

I couldn't resist noting my own unintentional cleverness here.
Many of vhdl's advantages are stolen from the language ADA.
Therefore, some are indeed "ada-advantages" ;)

        -- Mike Treseler

On Mon, 14 Sep 2009 12:05:22 -0700, Mike Treseler <mtreseler@gmail.com> wrote:

>Mike Treseler wrote:
>
>> Note that tested vhdl synthesis examples that
>> that make use of vhdl's unfair adavantages
>                                   advantages
>
>> as well as standard libraries, are rare.
>
>I couldn't resist noting my own unintentional cleverness here.
>Many of vhdl's advantages are stolen from the language ADA.
>Therefore, some are indeed "ada-advantages" ;)
>
I love those unintentional improvements (mutations? to the original word.

My favourite (unnoticed by its authors) was on a slide, presented by Motorola,
describing the features of a new chip - or rather, since they hadn't built it
yet - describing what they wanted us to believe the chip would do.

And the slide was titled...

Specifiction

- Brian