Hi All, I need to provide 8 clock outs shifted by 45 degree, clk_0 -> 0 degree phase shift clk_1 -> 45 degree phase shift clk_1 -> 90 degree phase shift clk_1 -> 135 degree phase shift clk_1 -> 180 degree phase shift clk_1 -> 225 degree phase shift clk_1 -> 270 degree phase shift clk_1 -> 315 degree phase shift clk_1 -> 360 degree phase shift Is it at all possible? Thanks in advance for your feed back. Qamrul
8 phase clock output
Started by ●September 14, 2009
Reply by ●September 15, 20092009-09-15
On Sep 15, 1:27=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote:> Hi All, > > I need to provide 8 clock outs shifted by 45 degree, > > clk_0 -> 0 degree phase shift > clk_1 -> 45 degree phase shift > clk_1 -> 90 degree phase shift > clk_1 -> 135 degree phase shift > clk_1 -> 180 degree phase shift > clk_1 -> 225 degree phase shift > clk_1 -> 270 degree phase shift > clk_1 -> 315 degree phase shift > clk_1 -> 360 degree phase shift > > Is it at all possible? > > Thanks in advance for your feed back. > > Qamrulyes
Reply by ●September 15, 20092009-09-15
On Mon, 14 Sep 2009 17:27:55 -0500, "qamrul" <qamrul.hasan@spansion.com> wrote:>Hi All, > >I need to provide 8 clock outs shifted by 45 degree, > >clk_0 -> 0 degree phase shift >clk_1 -> 45 degree phase shift >clk_1 -> 90 degree phase shift >clk_1 -> 135 degree phase shift >clk_1 -> 180 degree phase shift >clk_1 -> 225 degree phase shift >clk_1 -> 270 degree phase shift >clk_1 -> 315 degree phase shift >clk_1 -> 360 degree phase shift > >Is it at all possible?(almost) Anything is possible but not everything can be engineered. Depending on what you're going to do with it (and assuming you're using an FPGA) a PLL/DCM with 4 1/8 cycle delayed outputs and their inverses might work. If you are on an ASIC, you might get a PLL which gives you access to output of its delay line which would be what you need if you chose the right PLL. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●September 15, 20092009-09-15
Qamrul If you don't need super fast clock outputs, that is less than say 12-25 MHz, you can use an internal clock at X8, X16, and a clock enable structure to generate such outputs. If you take care such the outputs are "buffered" through an I/O register, running at the X8/16, then you won't get any significant skew on the phases due to routing. The clock enable can be a preloaded shift register, with wrap, that is loaded with X"0001" (X16) loaded at reset or other control condition. One thing that is ice about this way is that clocks can be "stopped" easily and restarted without any retraining or lock sequences. For higher frequencies using PLL or DLL techniques to achieve the required outputs is probably better. John Adair Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote:> Hi All, > > I need to provide 8 clock outs shifted by 45 degree, > > clk_0 -> 0 degree phase shift > clk_1 -> 45 degree phase shift > clk_1 -> 90 degree phase shift > clk_1 -> 135 degree phase shift > clk_1 -> 180 degree phase shift > clk_1 -> 225 degree phase shift > clk_1 -> 270 degree phase shift > clk_1 -> 315 degree phase shift > clk_1 -> 360 degree phase shift > > Is it at all possible? > > Thanks in advance for your feed back. > > Qamrul
Reply by ●September 15, 20092009-09-15
Thanks to all of you for useful feedback. My clock freq is 133 MHz. Based on your inputs and my understandig from reading "Spartan 3 FPGA Guide" this is what I plan to do. clk_i (main clock) connect it to one DCM input clock. 4 phased shifted output from the DCM will give me, clk90, clk180, clk 270. clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect it to another DCM input clock. 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, clk315. Am I in the right path? Each clock line drives only two FFs, is 133 MHz okay? How can I create "clk_i_inv_delayed" ? Best regards, Qamrul>Qamrul > >If you don't need super fast clock outputs, that is less than say >12-25 MHz, you can use an internal clock at X8, X16, and a clock >enable structure to generate such outputs. If you take care such the >outputs are "buffered" through an I/O register, running at the X8/16, >then you won't get any significant skew on the phases due to routing. > >The clock enable can be a preloaded shift register, with wrap, that is >loaded with X"0001" (X16) loaded at reset or other control condition. >One thing that is ice about this way is that clocks can be "stopped" >easily and restarted without any retraining or lock sequences. > >For higher frequencies using PLL or DLL techniques to achieve the >required outputs is probably better. > >John Adair >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: >> Hi All, >> >> I need to provide 8 clock outs shifted by 45 degree, >> >> clk_0 -> 0 degree phase shift >> clk_1 -> 45 degree phase shift >> clk_1 -> 90 degree phase shift >> clk_1 -> 135 degree phase shift >> clk_1 -> 180 degree phase shift >> clk_1 -> 225 degree phase shift >> clk_1 -> 270 degree phase shift >> clk_1 -> 315 degree phase shift >> clk_1 -> 360 degree phase shift >> >> Is it at all possible? >> >> Thanks in advance for your feed back. >> >> Qamrul > >--------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
Reply by ●September 15, 20092009-09-15
On Sep 15, 8:20=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote:> Thanks to all of you for useful feedback. > > My clock freq is 133 MHz. Based on your inputs and my understandig from > reading "Spartan 3 FPGA Guide" this is what I plan to do. > > clk_i (main clock) connect it to one DCM input clock. > 4 phased shifted output from the DCM will give me, clk90, clk180, clk > 270. > > clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connect i=t> to another DCM input clock. > > 4 phased shifted output from the DCM will give me, clk45, clk135, clk225, > clk315. > > Am I in the right path? Each clock line drives only two FFs, is 133 MHz > okay? > > How can I create "clk_i_inv_delayed" ? > > Best regards, > Qamrul > > > > >Qamrul > > >If you don't need super fast clock outputs, that is less than say > >12-25 MHz, you can use an internal clock at X8, X16, and a clock > >enable structure to generate such outputs. If you take care such the > >outputs are "buffered" through an I/O register, running at the X8/16, > >then you won't get any significant skew on the phases due to routing. > > >The clock enable can be a preloaded shift register, with wrap, that is > >loaded with X"0001" (X16) loaded at reset or other control condition. > >One thing that is ice about this way is that clocks can be "stopped" > >easily and restarted without any retraining or lock sequences. > > >For higher frequencies using PLL or DLL techniques to achieve the > >required outputs is probably better. > > >John Adair > >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> Hi All, > > >> I need to provide 8 clock outs shifted by 45 degree, > > >> clk_0 -> 0 degree phase shift > >> clk_1 -> 45 degree phase shift > >> clk_1 -> 90 degree phase shift > >> clk_1 -> 135 degree phase shift > >> clk_1 -> 180 degree phase shift > >> clk_1 -> 225 degree phase shift > >> clk_1 -> 270 degree phase shift > >> clk_1 -> 315 degree phase shift > >> clk_1 -> 360 degree phase shift > > >> Is it at all possible? > > >> Thanks in advance for your feed back. > > >> Qamrul > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www=.FPGARelated.com you are trying todo something that you should not. why do you need those clock phases? Antti
Reply by ●September 15, 20092009-09-15
you are trying todo something that you should not. why do you need those clock phases? Antti I am trying to capture DATA which comes into FPGA with skew and jitter. I need to sample this data with 8 phase shifted clock and need to find the correct data through pattern matching and training. Please explain why I should not do this? Any other better way?>On Sep 15, 8:20=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: >> Thanks to all of you for useful feedback. >> >> My clock freq is 133 MHz. Based on your inputs and my understandigfrom>> reading "Spartan 3 FPGA Guide" this is what I plan to do. >> >> clk_i (main clock) connect it to one DCM input clock. >> 4 phased shifted output from the DCM will give me, clk90, clk180, clk >> 270. >> >> clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connecti=>t >> to another DCM input clock. >> >> 4 phased shifted output from the DCM will give me, clk45, clk135,clk225,>> clk315. >> >> Am I in the right path? Each clock line drives only two FFs, is 133MHz>> okay? >> >> How can I create "clk_i_inv_delayed" ? >> >> Best regards, >> Qamrul >> >> >> >> >Qamrul >> >> >If you don't need super fast clock outputs, that is less than say >> >12-25 MHz, you can use an internal clock at X8, X16, and a clock >> >enable structure to generate such outputs. If you take care such the >> >outputs are "buffered" through an I/O register, running at the X8/16, >> >then you won't get any significant skew on the phases due to routing. >> >> >The clock enable can be a preloaded shift register, with wrap, thatis>> >loaded with X"0001" (X16) loaded at reset or other control condition. >> >One thing that is ice about this way is that clocks can be "stopped" >> >easily and restarted without any retraining or lock sequences. >> >> >For higher frequencies using PLL or DLL techniques to achieve the >> >required outputs is probably better. >> >> >John Adair >> >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. >> >> >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: >> >> Hi All, >> >> >> I need to provide 8 clock outs shifted by 45 degree, >> >> >> clk_0 -> 0 degree phase shift >> >> clk_1 -> 45 degree phase shift >> >> clk_1 -> 90 degree phase shift >> >> clk_1 -> 135 degree phase shift >> >> clk_1 -> 180 degree phase shift >> >> clk_1 -> 225 degree phase shift >> >> clk_1 -> 270 degree phase shift >> >> clk_1 -> 315 degree phase shift >> >> clk_1 -> 360 degree phase shift >> >> >> Is it at all possible? >> >> >> Thanks in advance for your feed back. >> >> >> Qamrul >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> This message was sent using the comp.arch.fpga web interfaceonhttp://www=>.FPGARelated.com > > > > >--------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
Reply by ●September 15, 20092009-09-15
On Tue, 15 Sep 2009 12:43:25 -0500 "qamrul" <qamrul.hasan@spansion.com> wrote:> > [snip] > > you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and > jitter. I need to sample this data with 8 phase shifted clock and > need to find the correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? >Sure. You could just have one clock phase coming out of the DCM, and use the variable phase shift to get the phase right dynamically. This will give you better phase resolution and a simpler circuit. Though managing to "train" the proper phase shift is left as a serious exercise for the student. -- Rob Gaddi, Highland Technology Email address is currently out of order
Reply by ●September 15, 20092009-09-15
On Sep 15, 8:43=A0pm, "qamrul" <qamrul.ha...@spansion.com> wrote:> you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and jitter. I > need to sample this data with 8 phase shifted clock and need to find the > correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way? > > > > > > >On Sep 15, 8:20=3DA0pm, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> Thanks to all of you for useful feedback. > > >> My clock freq is 133 MHz. Based on your inputs and my understandig > from > >> reading "Spartan 3 FPGA Guide" this is what I plan to do. > > >> clk_i (main clock) connect it to one DCM input clock. > >> 4 phased shifted output from the DCM will give me, clk90, clk180, clk > >> 270. > > >> clk_i_inv_delayed ( inverted main clock delayed by 22.5 degree) connec=t> i=3D > >t > >> to another DCM input clock. > > >> 4 phased shifted output from the DCM will give me, clk45, clk135, > clk225, > >> clk315. > > >> Am I in the right path? Each clock line drives only two FFs, is 133 > MHz > >> okay? > > >> How can I create "clk_i_inv_delayed" ? > > >> Best regards, > >> Qamrul > > >> >Qamrul > > >> >If you don't need super fast clock outputs, that is less than say > >> >12-25 MHz, you can use an internal clock at X8, X16, and a clock > >> >enable structure to generate such outputs. If you take care such the > >> >outputs are "buffered" through an I/O register, running at the X8/16, > >> >then you won't get any significant skew on the phases due to routing. > > >> >The clock enable can be a preloaded shift register, with wrap, that > is > >> >loaded with X"0001" (X16) loaded at reset or other control condition. > >> >One thing that is ice about this way is that clocks can be "stopped" > >> >easily and restarted without any retraining or lock sequences. > > >> >For higher frequencies using PLL or DLL techniques to achieve the > >> >required outputs is probably better. > > >> >John Adair > >> >Enterpoint Ltd. - Home of Drigmorn3. The Spartan-6 Starter Board. > > >> >On 14 Sep, 23:27, "qamrul" <qamrul.ha...@spansion.com> wrote: > >> >> Hi All, > > >> >> I need to provide 8 clock outs shifted by 45 degree, > > >> >> clk_0 -> 0 degree phase shift > >> >> clk_1 -> 45 degree phase shift > >> >> clk_1 -> 90 degree phase shift > >> >> clk_1 -> 135 degree phase shift > >> >> clk_1 -> 180 degree phase shift > >> >> clk_1 -> 225 degree phase shift > >> >> clk_1 -> 270 degree phase shift > >> >> clk_1 -> 315 degree phase shift > >> >> clk_1 -> 360 degree phase shift > > >> >> Is it at all possible? > > >> >> Thanks in advance for your feed back. > > >> >> Qamrul > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> This message was sent using the comp.arch.fpga web interface > onhttp://www=3D > >.FPGARelated.com > > --------------------------------------- =A0 =A0 =A0 =A0 > This message was sent using the comp.arch.fpga web interface onhttp://www=.FPGARelated.com ISERDES IDELAY
Reply by ●September 15, 20092009-09-15
On Sep 15, 10:43=A0am, "qamrul" <qamrul.ha...@spansion.com> wrote:> you are trying todo something that you should not. > > why do you need those clock phases? > > Antti > > I am trying to capture DATA which comes into FPGA with skew and jitter. I > need to sample this data with 8 phase shifted clock and need to find the > correct data through pattern matching and training. > > Please explain why I should not do this? Any other better way?RTFM for Xilinx Virtex4 and 5 "SelectIO" ILOGIC blocks. It can do what you want without the ridiculous stuff you think you need.
