FPGA for acoustic adaptive beamforming

Hi,

i'm not an expert user of FPGA but i need to solve a problem before
starting to work on it.
I have to choose an FPGA to implement an acoustic beam forming. My
system has 512 input channels (microphones). After A/D conversion at
48 KHz with 24 bit per sample i need to have all the 512 signals
syncronysed to perform the beamforming. So far i have read that Xilinx
tools and FPGA (Spartan or Virtex) should fix my problem but i have
difficulties in choosing the right model.
From a SW point of view I'd like to implement my model on Simulik,
translate it into VHDL and then put the code into FPGA. DO you think
that Xilinx products could solve my problem and which model do you
suggest to buy?
The FPGA + SW at about what price is sold? Please any suggestion could
be very useful for me. Thanks in advance for your help.

"DOD" <domenicodonisi@libero.it> wrote in message 
news:f2edb08f-7467-4e41-8843-6ff3d9567b8e@j9g2000vbp.googlegroups.com...
> Hi,
>
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at
> 48 KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model.
> From a SW point of view I'd like to implement my model on Simulik,
> translate it into VHDL and then put the code into FPGA. DO you think
> that Xilinx products could solve my problem and which model do you
> suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help.


You are picking a pretty big job for your first FPGA - what's wrong with 
traffic lights like everyone else ?

Seriously, you may be confusing developing with an FPGA with writing code 
for a processor.  Although Xilinx and the Mathworks offer a Simulink to FPGA 
path don't expect it to be easy or do all the work for you.
You can (should) get the software before you buy any hardware and work out 
how much FPGA the design will need. You can start with some fairly cheap 
tools from Xilinx (check on their website) but in the end you will need 
MATLAB, SIMULINK and other licenses from the Mathworks (expect about $10k 
last time I looked).

Michael Kellett

DOD wrote:

> Hi,
> 
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at 48
> KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model. From a SW point of view I'd
> like to implement my model on Simulik, translate it into VHDL and then
> put the code into FPGA. DO you think that Xilinx products could solve my
> problem and which model do you suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help.

Yes, this sort of problem can be solved in an FPGA, and Xilinx has 
software to translate from a Simulink model into VHDL. I've used it, it 
works.

List price for the software "DSP Edition" is about USD $4000 for a node 
locked license. Of course MatLab is also required, which will cost about 
twice as much or more depending on options selected. If your application 
is for University, sizable discounts are available for both software 
packages.

The size FPGA required is very hard to estimate, as there are a lot of 
details needed.

It would make sense to spend a lot of time developing the design before 
choosing a part to get a good idea of the minimum cost FPGA than can do 
all the required functions.

What are the requirements? There are a lot of different application 
requirements under the general category of beamforming. Some would fit in 
the larger Spartan parts. Some would require more resources. Some could 
be done in software only, or some combination of hardware processing and 
software processing. Frequency or time domain? Adaptive, prefiltering, 
noise reduction or echo cancellation per channel? Number of beams? Focus? 
Shape of array? All can change the amount and type of resources required.


-- 
Phil Hays
(phil_hays at eeei.gro (fix the order for email)

What is the algorithm you need to perform on the 512 samples every 20 micro 
seconds.  Do you just need to move their zero crossing's of the inputs to 
some common time at the output, or is there more involved.

What accuracy do you need in time and amplitude for your output?

What type of latency do you need between a given input and the corresponding 
effect on its output?

-- 
Marco
UCO Lick Observatory
Laboratory for Adaptive Optics

"DOD" <domenicodonisi@libero.it> wrote in message 
news:f2edb08f-7467-4e41-8843-6ff3d9567b8e@j9g2000vbp.googlegroups.com...
> Hi,
>
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at
> 48 KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model.
> From a SW point of view I'd like to implement my model on Simulik,
> translate it into VHDL and then put the code into FPGA. DO you think
> that Xilinx products could solve my problem and which model do you
> suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help. 

On Fri, 18 Sep 2009 18:26:49 GMT, phil hays <philhays@dont.spam> wrote:

[snippety snip]
>The size FPGA required is very hard to estimate, as there are a lot of 
>details needed.
>
>It would make sense to spend a lot of time developing the design before 
>choosing a part to get a good idea of the minimum cost FPGA than can do 
>all the required functions.

Or develop on the biggest, fastest, meanest dev board that's at least
several times larger, faster, etc. than a back of the envelope estimate
would suggest. Place'n'route is faster, there's room for debugging hooks
and sniffers, and also for the inevitable feature creep.

After the dust settles and everybody signs-off on the prototype, and if
the volume and cost models support it, then it may be time to squeeze
the design into the cheapest silicon.

If it's a low production rate item -- ten a year, not 10,000 per week --
the silicon cost may not even be a rounding error in the final unit cost
and it might make sense to stay with a roomier chip.

>What are the requirements? There are a lot of different application 
>requirements under the general category of beamforming. Some would fit in 
>the larger Spartan parts. Some would require more resources. Some could 
>be done in software only, or some combination of hardware processing and 
>software processing. Frequency or time domain? Adaptive, prefiltering, 
>noise reduction or echo cancellation per channel? Number of beams? Focus? 
>Shape of array? All can change the amount and type of resources required.

Well, the back of a *large* envelope ...

-- 
Rich Webb     Norfolk, VA

Can you elaborate on your problem? For example, if you are looking to 
capture 512 signals in parallel no one FPGA is going to provide the 12,288 
data lines needed to have 24 bit samples directly connected from 512 ADC 
chips. I would suggest using some combination of analog multiplexing and a 
ADC running at a much higher rate than 48KHz to capture frames of each 
channel then use the FPGA to demux the digital data into multiple streams. 
The ADCs can be synced using a master clock for parallel capturing. If you 
are recording samples from multiple sources, i.e. different computers on a 
network, you may want to drop the least significant bit and insert a time 
stamp that covers 8-16 samples. You can get examples of timing stamps using 
framing standards from most telecommunication protocols. Either means of 
capturing data will place a overhead on the FPGA to decode the samples and 
sync them. Because you are working with 512 signals the decoding/syncing 
overhead will not be a minor block of your design. The bandwidth would be 
around 73.7MB for your specification, so you will not even be able to use a 
USB based board to transfer the samples to/from a computer. A PCIe board 
would give you the band width to capture 512 signals.

The key point I am making is you will not be able to find one product to 
fill your bill. You would be better off starting with 32 to 64 signals. If 
you are not flexible on the 512 signals, you may want to look at creating a 
capture board for capturing the signals and inserting a time stamp then use 
a supercluster from www.picocomputing.com to process the signals. This will 
break most budgets placed on academic projects, so I hope you have deep 
pockets.

"DOD" <domenicodonisi@libero.it> wrote in message 
news:f2edb08f-7467-4e41-8843-6ff3d9567b8e@j9g2000vbp.googlegroups.com..
> Hi,
>
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.
> I have to choose an FPGA to implement an acoustic beam forming. My
> system has 512 input channels (microphones). After A/D conversion at
> 48 KHz with 24 bit per sample i need to have all the 512 signals
> syncronysed to perform the beamforming. So far i have read that Xilinx
> tools and FPGA (Spartan or Virtex) should fix my problem but i have
> difficulties in choosing the right model.
> From a SW point of view I'd like to implement my model on Simulik,
> translate it into VHDL and then put the code into FPGA. DO you think
> that Xilinx products could solve my problem and which model do you
> suggest to buy?
> The FPGA + SW at about what price is sold? Please any suggestion could
> be very useful for me. Thanks in advance for your help. 

Aio wrote:

> Can you elaborate on your problem? For example, if you are looking to
> capture 512 signals in parallel no one FPGA is going to provide the
> 12,288 data lines needed to have 24 bit samples directly connected from
> 512 ADC chips.

ADC chips used for audio often have a serial interface I2S, with two 
channels on one serial line. That would require 256 data lines plus a 
word select line plus a clock, easy for a midsize or larger Spartan.

http://en.wikipedia.org/wiki/I%C2%B2S


-- 
Phil Hays
(phil_hays at eeei.gro (fix the order for email)

You would add a lot of overhead to the design using 256 I2S interfaces. The 
FPGA real-estate devoted to decoding 256 I2S connections is substantial, 
even though you can find ready made IPCores to decode the I2S signals.  Note 
the original question was from someone that stated they were not a expert 
with FPGAs, so a development board would be the best solution, but you will 
have to look hard for a development board with 256 accessible data lines.

To create a design that would work with almost all commercial development 
boards, I would setup a state machine that used 24 data line input and 
cycles through 512 states demultiplexing the input. To make it work you 
would need 8 identical ADC using a two stage analog multiplexers. The output 
from the ADC is connected to 8to1 24bit multiplexer to connect to the FPGA. 
You could run the multiplexers to generate a  frame of  512 24 bit samples 
that are synchronized. This setup will reduce the BOM size not to mention 
the overhead for the state machine is much less than decoding 256 I2S 
interfaces. The down side to the setup is the timing complexity, but 
everything has a trade off.

example of one ADC setup
analog multiplexer to ADC
16to1 -\
16to1 -|__ 4to1--ADC  ~3Msps
16to1 -|
16to1 -/


"phil hays" <philhays@dont.spam> wrote in message 
news:1fUsm.2691$Jd7.1421@nwrddc02.gnilink.net...
> Aio wrote:
>
>> Can you elaborate on your problem? For example, if you are looking to
>> capture 512 signals in parallel no one FPGA is going to provide the
>> 12,288 data lines needed to have 24 bit samples directly connected from
>> 512 ADC chips.
>
> ADC chips used for audio often have a serial interface I2S, with two
> channels on one serial line. That would require 256 data lines plus a
> word select line plus a clock, easy for a midsize or larger Spartan.
>
> http://en.wikipedia.org/wiki/I%C2%B2S
>
>
> -- 
> Phil Hays
> (phil_hays at eeei.gro (fix the order for email) 

phil hays wrote:
> Aio wrote:
> 
>> Can you elaborate on your problem? For example, if you are looking to
>> capture 512 signals in parallel no one FPGA is going to provide the
>> 12,288 data lines needed to have 24 bit samples directly connected from
>> 512 ADC chips.
> 
> ADC chips used for audio often have a serial interface I2S, with two 
> channels on one serial line. That would require 256 data lines plus a 
> word select line plus a clock, easy for a midsize or larger Spartan.
> 
> http://en.wikipedia.org/wiki/I%C2%B2S
> 
> 

Texas Instruments has an 8 channel, simultaneous sampling (up to 
144kHz), 24 bit serial output A/D: look up the ADS1278.  Your 512 
channels would require 64 devices.  While the channels are sampled 
simultaneously they are transmitted in sequence on a single serial 
output. The clocks and strobes can be driven in parallel, so you'd only 
need 64 input pins and just a few outputs.  Your 48kHz sample rate would 
translate into a 9.2MHz serial data rate, but that's not to difficult 
for an FPGA.

Of course that part is $35 at DigiKey, so you'd be spending a couple 
thousand dollars on the A/Ds alone...

Chris Abele

DOD <domenicodonisi@libero.it> wrote:
 
> i'm not an expert user of FPGA but i need to solve a problem before
> starting to work on it.

I suggest a systolic array.  Without knowing what computation you
want to perform it is hard to say, but systolic arrays work for
a variety of such processing problems.

-- glen