timing simulation performance

Hi,

when starting a netlist simulation (vho) with timing file (sdf) what
is the
saving in simulation time when simulating a small 8bit counter

a) on a netlist which represents an CPLD being 90% filled
b) on a netlist which represents an CPLD being 3% filled

Does the simulation take the same simulation duration (real time) ? I
mean the vho file has to be compiled anyway.

Rgds,
Hssig

hssig <hssig@gmx.net> wrote:
 
< when starting a netlist simulation (vho) with timing file (sdf) what
< is the
< saving in simulation time when simulating a small 8bit counter
 
< a) on a netlist which represents an CPLD being 90% filled
< b) on a netlist which represents an CPLD being 3% filled
 
< Does the simulation take the same simulation duration (real time) ? I
< mean the vho file has to be compiled anyway.

Place and Route takes a lot longer for 90% full.  

I would expect the simulation time not to change much, though
maybe a little bit.  With the usual event driven simulation,
there might be some glitches that propagate through the logic
as the signals change, and those might affect the timing in
different ways.  For synchronous logic, the signals are expected
to settle to the final value before the next clock, but the time
needed for simulation could be different.

-- glen

Hi Glen,

thank you for your answer.
The 8bit counter "coexists" with the rest of the design, that means
there is no dependency.
Does it have an influence on the simulation duration if the

a) the "rest" of the design is not activated in simulation
b) the "rest" of the design is frequently toggling  ?

What exactly leads to a slowdown in gate-level simulation ? Are the
events on the gates the time consuming factor ?

Rgds,

Hssig

hssig wrote:

> Does the simulation take the same simulation duration (real time) ? I
> mean the vho file has to be compiled anyway.

And recompiled every time I make the slightest change.

If I were testing a synchronous counter, I would
sim the .vhd file directly.

I would only make a .vho if I were testing Quartus.

           -- Mike Treseler

Hi Mike,


yes, I know. But I am trying to understand under which circumstances a
gate-level simulation gets slow
and whether it makes a difference how many gates are simulated.

Rgds,

Hssig

hssig wrote:

> yes, I know. But I am trying to understand under which circumstances a
> gate-level simulation gets slow
> and whether it makes a difference how many gates are simulated.

A .vho netlist is composed of altera primitives like luts and flops,
not gates, so I'm not sure what the question means.

I have never made an exact measurement of netlist sims, but I would
guess that they average ten times slower than code.

          -- Mike Treseler

On Mon, 21 Sep 2009 14:17:20 -0700 (PDT), hssig <hssig@gmx.net> wrote:

>Hi Mike,
>
>
>yes, I know. But I am trying to understand under which circumstances a
>gate-level simulation gets slow

Back-annotated gate-level simulations are much slower than simple
behavioral gate-level simulations. If you are using gate level sims as
a replacement for formal verification, this might make sense for you.
Check  out +nospecify option in your simulator.

>and whether it makes a difference how many gates are simulated.

All event based simulators become slower as the number of events go
up. More gates usually mean more events so larger designs usually
simulate more slowly whether they're RTL or gate-level sims.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

On Mon, 21 Sep 2009 14:17:20 -0700 (PDT), hssig wrote:

>...I am trying to understand under which circumstances a
>gate-level simulation gets slow

Almost all circumstances :-)

As you speculated in another post, it's all the events
on all those single-bit signals that makes everything 
so slow.  A gate-level simulation is a very large number
of parallel processes (gate descriptions), each of which
does very little work; it's the communication between them
(triggering of activity because of signal transitions)
that costs the simulator so much work.

>and whether it makes a difference how many gates are simulated.

Of course it does!  The processing of signal events dominates
the computation.  The number of events per simulated clock
cycle will scale (very roughly) linearly with the number of
gates.  More gates -> slower.

Adding timing backannotation with an SDF file will add 
another performance hit, because each signal event then
gives rise to a bunch more work computing delays, timing
checks and so forth.

Of course, simulator vendors work hard to optimize all
this stuff for performance.  But it's still waaaaaay slow
by comparison with RTL simulation, in which there are
many fewer events and each event does much more work
(more complex computations in each process).  Go to
a very abstract transaction-level model of your system
and you should expect to see yet another couple of 
orders of magnitude of speedup, hence the trend towards
C++ or SystemC modelling of large systems at early stages
in the design cycle.
-- 
Jonathan Bromley, Consultant

DOULOS - Developing Design Know-how
VHDL * Verilog * SystemC * e * Perl * Tcl/Tk * Project Services

Doulos Ltd., 22 Market Place, Ringwood, BH24 1AW, UK
jonathan.bromley@MYCOMPANY.com
http://www.MYCOMPANY.com

The contents of this message may contain personal views which 
are not the views of Doulos Ltd., unless specifically stated.

On Mon, 21 Sep 2009 14:44:03 -0700, Mike Treseler
<mtreseler@gmail.com> wrote:

>hssig wrote:
>
>> yes, I know. But I am trying to understand under which circumstances a
>> gate-level simulation gets slow
>> and whether it makes a difference how many gates are simulated.
>
>A .vho netlist is composed of altera primitives like luts and flops,
>not gates, so I'm not sure what the question means.

An ASIC gate level netlist is composed of the primitives in the
standard cell library like complex functions (AOI221 etc. ) and flops
which is not all that different from the LUT and flops in an fpga gate
level netlist. It's definitely possible to write a specialized
definition for every initialization of a LUT to convert it from a LUT
based netlist to a "gate" based netlist.
-- 
Muzaffer Kal

DSPIA INC.
ASIC/FPGA Design Services

http://www.dspia.com

Hi Jonathan,

thank you for explaining, it becomes clear now.

Rgds,
Hssig