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view memory contents in modelsim

Started by hariz September 22, 2009
i am just a new user of modelsim and debussy, can anyone help me transfer
my code to modelsim and debussy from quartus?

i have a code in verilog using quartus..but due to long simulation time i
can't view all the output..so i switched to modelsim..however, i cant view
the memory contents in modelsim..

how can i double check the contents of my memory in modelsim?


hariz wrote:
> i am just a new user of modelsim and debussy, can anyone help me transfer > my code to modelsim and debussy from quartus? > > i have a code in verilog using quartus..but due to long simulation time i > can't view all the output..so i switched to modelsim..however, i cant view > the memory contents in modelsim.. > > how can i double check the contents of my memory in modelsim? > >
I add the memory array variable or signal to the waveforms. If I leave the mouse arrow over the array waveform, a table of values pops up for each clock tick. Or just have the testbench write some values and read them back. -- Mike Treseler
hariz wrote:
> i am just a new user of modelsim and debussy, can anyone help me transfer > my code to modelsim and debussy from quartus?
Where do you need debussy with Modelsim. Most of the debussy features are already in normal Modelsim gui.
> how can i double check the contents of my memory in modelsim?
There are many ways, one is to use in the workspace pane Memory tab and find the memory array there. Or in the objects window right click the memory array and select "View memory contents". If you need to modify the contents etc. that can be done via the memory viewer or via tcl commands in scripts. Remember to make sure that you have enough visibility (-novopt or +acc in vopt flow). --Kim
Mike Treseler wrote:
> I add the memory array variable or signal to the waveforms. > If I leave the mouse arrow over the array waveform, > a table of values pops up for each clock tick.
If the memory is done in VHDL signals/variables this slows down the simulation considerably. On the other hand if the memory is done in verilog the simulation does not slow down. Only verilog has optimizations in this area. Just small tip if simulation performance is needed ;) --Kim