What is the basis on flip-flop replaced by a latch

Hi,
I am interested in reading the post on "ASIC Prototyping using FPGA"
in which it mentioned that in ASIC, flip-flops are used to be replaced
with latchs.

I cound't understand it.

For example, a state machine. If FFs are used, after the next clock
pulse, FFs change status. If latches are used, I don't know how the
latches can be kept unchanged while code outside the state machine is
using the state information.

anyone would like to expain it more in details?

Thank you.

Weng

Weng Tianxiang <wtxwtx@gmail.com> wrote:

< I am interested in reading the post on "ASIC Prototyping using FPGA"
< in which it mentioned that in ASIC, flip-flops are used to be replaced
< with latchs.
 
< I cound't understand it.
 
< For example, a state machine. If FFs are used, after the next clock
< pulse, FFs change status. If latches are used, I don't know how the
< latches can be kept unchanged while code outside the state machine is
< using the state information.
 
< anyone would like to expain it more in details?

I agree.  As far as I know, ASIC libraries use the same type
of edge triggered FF's as FPGAs.  Well, in the old days people
used to do strange things, like dynamic logic.  The 8080 and 8086
have minimum clock rates, as the registers will lose their
contents if you clock too slow.  When the Z80 came out with
static logic people were much happier.  (You can slow the clock
down and watch instructions execute one at a time.)

Also, with a two phase clock you can use simpler latches, but as
far as I know, that isn't the way current logic works.

-- glen

On Oct 14, 10:56=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
> Weng Tianxiang <wtx...@gmail.com> wrote:
>
> < I am interested in reading the post on "ASIC Prototyping using FPGA"
> < in which it mentioned that in ASIC, flip-flops are used to be replaced
> < with latchs.
>
> < I cound't understand it.
>
> < For example, a state machine. If FFs are used, after the next clock
> < pulse, FFs change status. If latches are used, I don't know how the
> < latches can be kept unchanged while code outside the state machine is
> < using the state information.
>
> < anyone would like to expain it more in details?
>
> I agree. =A0As far as I know, ASIC libraries use the same type
> of edge triggered FF's as FPGAs. =A0Well, in the old days people
> used to do strange things, like dynamic logic. =A0The 8080 and 8086
> have minimum clock rates, as the registers will lose their
> contents if you clock too slow. =A0When the Z80 came out with
> static logic people were much happier. =A0(You can slow the clock
> down and watch instructions execute one at a time.)
>
> Also, with a two phase clock you can use simpler latches, but as
> far as I know, that isn't the way current logic works.
>
> -- glen

Hi glen,
Thank you for your comments.
I have a great relief, otherwise all of my knowledge of the digital
circuit designs would be useless if latchs would overwhelm the FFs. In
all my 10 digital circuit designs, I have never used a latch.

The only legal and valuable use of a latch I have learned was from an
asynchronous FIFO design by Peter and Conning.

Weng

Weng Tianxiang <wtxwtx@gmail.com> wrote:
(big snip)

< Thank you for your comments.

< I have a great relief, otherwise all of my knowledge of the digital
< circuit designs would be useless if latchs would overwhelm the FFs. In
< all my 10 digital circuit designs, I have never used a latch.
 
< The only legal and valuable use of a latch I have learned was from an
< asynchronous FIFO design by Peter and Conning.

These days most of the time latch means the same thing as FF.
For the other kind, the term transparent latch should be used.

In the TTL days, you could put a transparent latch between a
counter and a 7447 seven segment decoder.  Then it works like
the lap timer on a stopwatch where you can latch the count
while the counter runs, or watch the counter output.

I suppose I can also see it for a FIFO, especially if the
FIFO is required to pass the input directly to the output
when it is empty.  

-- glen

On Oct 14, 12:47=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
wrote:
>
> These days most of the time latch means the same thing as FF.
> For the other kind, the term transparent latch should be used.
>

My theory is that latches are only used by two extreme classes of
designers:

Very savvy and experienced ones, when faced with tough timing and
asynchronous issues.
Or
Very naive ones that do not fully appreciate the robust beauty of the
edge-triggered flip-flop.

The rest of the world happily uses flip-flops.

Peter Alfke, speaking for himself.

On Oct 14, 8:25=A0pm, Peter Alfke <al...@sbcglobal.net> wrote:
> On Oct 14, 12:47=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu>
> wrote:
>
>
>
> > These days most of the time latch means the same thing as FF.
> > For the other kind, the term transparent latch should be used.
>
> My theory is that latches are only used by two extreme classes of
> designers:
>
> Very savvy and experienced ones, when faced with tough timing and
> asynchronous issues.
> Or
> Very naive ones that do not fully appreciate the robust beauty of the
> edge-triggered flip-flop.
>
> The rest of the world happily uses flip-flops.
>
> Peter Alfke, speaking for himself.

Hi Peter,
!!! Excellent and sharp point !!!

Have you seen the post  "ASIC Prototyping using FPGA" ? Please give a
comment over there.

I had wondered that ASIC has another new type of logic to overwhelm
use latches over flip-flops.

Weng

Peter Alfke <alfke@sbcglobal.net> wrote:
<? On Oct 14, 12:47?pm, glen herrmannsfeldt wrote:

<?> These days most of the time latch means the same thing as FF.
<?> For the other kind, the term transparent latch should be used.

<? My theory is that latches are only used by two extreme classes of
<? designers:
 
<? Very savvy and experienced ones, when faced with tough timing and
<? asynchronous issues.
<? Or
<? Very naive ones that do not fully appreciate the robust beauty of the
<? edge-triggered flip-flop.

Yes that sounds about right.  I have wondered what all tricks
Intel used in the 8080 to do what it does with so few transistors,
and then for the 8086.  The 8086 is especially tricky with a
two phase clock with 33% duty cycle (for full speed operation).

I was once wondering why no FPGAs implement the Earle Latch:

http://books.google.com/books?id=QR9px-K6qxkC&pg=PA25&lpg=PA25&dq=%22earle+latch%22&source=bl&ots=d522CUmFuO&sig=9Ktu3pygcAoKCRgdDj0B7103H8A&hl=en&ei=VKnWSu-LAo7sMcaqyNEI&sa=X&oi=book_result&ct=result&resnum=4&ved=0CBUQ6AEwAw#v=onepage&q=%22earle%20latch%22&f=false

though that would likely only apply to the first category listed above.
(Also, it adds the complication of distributing a two phase clock.)

I believe it was designed by IBM for the 360/91.

-- glen

On Oct 14, 11:40=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:

> I had wondered that ASIC has another new type of logic to overwhelm
> use latches over flip-flops.
>

I believe the motivation for the general liking of latches rather than
flip flops in the ASIC world is power consumption.  That clock net
consumes a sizable chunk of power whether that flip flop actually
changes state or not.

Just because FPGAs have to cobble together logic to create a latch
(and cause potential timing issues in doing so) and that they are not
appropriate storage elements in all cases are only reasons why use of
latches in FPGAs and CPLDs is usually not a good path to head down.
Not all designs live in that world with those constraints.  ASIC
worlds have a different set of constraints to live within.  Don't
assume that the ASIC folks don't use the appropriate storage element,
just accept that they may not be constrained from using ones that
would not work well in a different environment such as an FPGA.

KJ

All,

A good paper was presented In Monterey FPGA conference 2009 from
Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom
processor before layout.

One of the things they talk about is how their ASIC standard cell/
custom flow uses Latches for speed and power improvements (over the
use of edge triggered flip flops).

If you want to learn about why someone would use latches in an ASIC, I
suggest reading this paper.

I also suggest reading this paper if you have to test your ASIC design
before you tapeout, as it talks about converting the latches back to
edge-triggered flip flops, and all the other "gothcahs" that people
commonly face.

All in all, the 70 million transistor Atom core, less cache memories
(left with 14 million transistors) fit in the LX330, and operated fast
enough to boot operating systems, browse web pages, etc.

http://www.ece.wisc.edu/~kati/fpga2009/index.html

(Hi Peter!  Hows the vines growing?)

Austin

On Oct 15, 10:02=A0am, austin <aus...@xilinx.com> wrote:
> All,
>
> A good paper was presented In Monterey FPGA conference 2009 from
> Intel, on their use of a Xilinx Virtex 5 LX330 to test their Atom
> processor before layout.
>
> One of the things they talk about is how their ASIC standard cell/
> custom flow uses Latches for speed and power improvements (over the
> use of edge triggered flip flops).
>
> If you want to learn about why someone would use latches in an ASIC, I
> suggest reading this paper.
>
> I also suggest reading this paper if you have to test your ASIC design
> before you tapeout, as it talks about converting the latches back to
> edge-triggered flip flops, and all the other "gothcahs" that people
> commonly face.
>
> All in all, the 70 million transistor Atom core, less cache memories
> (left with 14 million transistors) fit in the LX330, and operated fast
> enough to boot operating systems, browse web pages, etc.
>
> http://www.ece.wisc.edu/~kati/fpga2009/index.html
>
> (Hi Peter! =A0Hows the vines growing?)
>
> Austin

Hi Austin,
Where is the paper? or its title, or authors?

What you mentioned is what I am interested in.

Weng