I am trying to simulate in Modelsim XE web edition a verilog only project consisting of top level and few components. All components have same time resolution units and have wire type outputs. The problem is that Modelsim doesn't recognise the drive of any component's output connected to another's input. Yet it accepts the drive when connected to an output at toplevel itself. What am I missing here? Is there anything else to do about binding? Any help appreciated. This problem does not occur with vhdl projects. kadhiem --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
ModelSim fails to connect my project components
Started by ●October 16, 2009
Reply by ●October 16, 20092009-10-16
kadhiem_ayob wrote:> I am trying to simulate in Modelsim XE web edition a verilog only project > consisting of top level and few components. All components have same time > resolution units and have wire type outputs. The problem is that Modelsim > doesn't recognise the drive of any component's output connected to > another's input. Yet it accepts the drive when connected to an output at > toplevel itself.http://www.sutherland-hdl.com/online_verilog_ref_guide/vlog_ref_body.html#8.0%20Module%20Instances