ISe 10.1 nightmare bug

I have SP3 installed in the 10.1 -  but sometimes - once a while, the
entire project just corrupted - when "rerun all" it TOOK the topmodule
source from "nowhere" - nomatter how you change your topmodule it
still lock the topmodule source fom that mystery source

Oh my goodness

On Oct 23, 10:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source
>
> Oh my goodness

I just had another ise 10.1 project nightmare too, it was a real
nightmare
ah yes, sometimes the project files did show files that well i have no
idea
where it got them, as the file did not have them, I updated a fresh
known
good copy of the ise file from SVN repo maybe 40 times, but each time
ISE did destroy the ise on opening or then displayed wrong content.

I know, upgrade to 11.x is a must, but for this project we can not do
it
so we are left to fight with the ISE nightmares

Antti

Mawa_fugo wrote:
> 
> I have SP3 installed in the 10.1 -  but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source

Create a new project and then copy all your design files from the old
to the new project. This requires only a few seconds and then you
can continue your work for a few hours before you have to create 
the next new project version. I really would like to have the good
old DOS development software back which they shipped for the XC3000
FPGA's twenty years ago.

On Oct 24, 3:35=A0am, Herbert Kleebauer <k...@unibwm.de> wrote:
> Mawa_fugo wrote:
>
> > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> > entire project just corrupted - when "rerun all" it TOOK the topmodule
> > source from "nowhere" - nomatter how you change your topmodule it
> > still lock the topmodule source fom that mystery source
>
> Create a new project and then copy all your design files from the old
> to the new project. This requires only a few seconds and then you
> can continue your work for a few hours before you have to create
> the next new project version. I really would like to have the good
> old DOS development software back which they shipped for the XC3000
> FPGA's twenty years ago.

Yup - that's the only way to overcome this nightmare - but for a
fairly big project it take some effort to make sure you ghosting the
exact project

On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> entire project just corrupted - when "rerun all" it TOOK the topmodule
> source from "nowhere" - nomatter how you change your topmodule it
> still lock the topmodule source fom that mystery source
>
> Oh my goodness

The "Cleanup Project Files" under the "Project" menu can solve many of
these problems.

kevin

On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
> On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
>
> > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, the
> > entire project just corrupted - when "rerun all" it TOOK the topmodule
> > source from "nowhere" - nomatter how you change your topmodule it
> > still lock the topmodule source fom that mystery source
>
> > Oh my goodness
>
> The "Cleanup Project Files" under the "Project" menu can solve many of
> these problems.
>
> kevin

Thanks for suggestion - it does something difference when I tried to
clean the project but it still lock the source from "nowhere"

You know what? I've just started a brand new project and copy every
single bit from the current design - it let me  play for a couple
rounds before doing exact the same thing

That's totally frustrating - fortunatly every time successfully
routing I backup rite away - btw/ the Xilinx snapshot does not help at
all - it restore the junk project

THis is a night mare

On Oct 26, 12:43=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
>
> > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
>
> > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t=
he
> > > entire project just corrupted - when "rerun all" it TOOK the topmodul=
e
> > > source from "nowhere" - nomatter how you change your topmodule it
> > > still lock the topmodule source fom that mystery source
>
> > > Oh my goodness
>
> > The "Cleanup Project Files" under the "Project" menu can solve many of
> > these problems.
>
> > kevin
>
> Thanks for suggestion - it does something difference when I tried to
> clean the project but it still lock the source from "nowhere"
>
> You know what? I've just started a brand new project and copy every
> single bit from the current design - it let me =A0play for a couple
> rounds before doing exact the same thing
>
> That's totally frustrating - fortunatly every time successfully
> routing I backup rite away - btw/ the Xilinx snapshot does not help at
> all - it restore the junk project
>
> THis is a night mare

If you hover over the file in the source pane it will display the path
to the source - verify that is correct.

Also be careful when adding the source to the project as there is an
option to "copy" the file to the project directory rather than using
it in place.

I have only had a problem once and the "cleanup project files" command
corrected it.

kevin

On Oct 26, 2:43=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
>
> > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
>
> > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t=
he
> > > entire project just corrupted - when "rerun all" it TOOK the topmodul=
e
> > > source from "nowhere" - nomatter how you change your topmodule it
> > > still lock the topmodule source fom that mystery source
>
> > > Oh my goodness
>
> > The "Cleanup Project Files" under the "Project" menu can solve many of
> > these problems.
>
> > kevin
>
> Thanks for suggestion - it does something difference when I tried to
> clean the project but it still lock the source from "nowhere"
>
> You know what? I've just started a brand new project and copy every
> single bit from the current design - it let me =A0play for a couple
> rounds before doing exact the same thing
>
> That's totally frustrating - fortunatly every time successfully
> routing I backup rite away - btw/ the Xilinx snapshot does not help at
> all - it restore the junk project
>
> THis is a night mare

I may doing somthing stupid here, but I found a way temporary to deal
with this night mare - In my project I always keep two top modules -
One is the real design (big circuit) and the other is a dummy
topmodule (just an input -ouput)

Now everytime I attemp to route the real desing - I switch to set
topmule as the dummy first - and run the XST first - if I see it route
quick (less than a minute)  then I know the XST doing ok - if it
synthesize the dummy with tons of nets and macros - then it lock to
the mystery topmodule source already.  If it happens thta way then I
would restore the archieve to save time chasing my own tail around

Wow, what a night mare

On Mon, 26 Oct 2009 12:43:12 -0700 (PDT)
Mawa_fugo <ccon67@netscape.net> wrote:

> On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
> > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
> >
> > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while, t=
he
> > > entire project just corrupted - when "rerun all" it TOOK the topmodule
> > > source from "nowhere" - nomatter how you change your topmodule it
> > > still lock the topmodule source fom that mystery source
> >
> > > Oh my goodness
> >
> > The "Cleanup Project Files" under the "Project" menu can solve many of
> > these problems.
> >
> > kevin
>=20
> Thanks for suggestion - it does something difference when I tried to
> clean the project but it still lock the source from "nowhere"


Hi

I also had to deal with the same kind of issue with ISE 10.1SP3: after chec=
king out a project stored on a version control system (SVN), the top-level =
mark disappeared and the "Set as Top Module" action was disabled.  Needless=
 to say that I tried all the usuals (amongst other things: "Cleanup Project=
 Files", "Check Syntax", removing/adding again the top-level source file) w=
ithout much success.

After a few minutes fiddling around, I tried to change the "Top-Level Sourc=
e Type" project property from HDL to EDIF and back to HDL --define long sho=
ot ;) -- and YGTBK! my top-level came back!


> THis is a night mare


At the very least it must scare some EEs away from FPGA design  ;)  One a m=
ore serious note, I'm still hoping that five years after the buyout of Hier=
 Design, the people behind Planahead didn't get brainwashed and would sugge=
st the rest of the Design Software Division at Xilinx to put some common se=
nse in ISE (such as using --again-- a text format for the project file).


--=20
Matthieu Michon <prenom.nom@gmail.com>

On Oct 27, 10:45=A0am, Matthieu Michon
<matthieu.d.u.m.m.y.mic...@gmail.com> wrote:
> On Mon, 26 Oct 2009 12:43:12 -0700 (PDT)
>
>
>
>
>
> Mawa_fugo <cco...@netscape.net> wrote:
> > On Oct 24, 11:51=A0am, kevin93 <ke...@whitedigs.com> wrote:
> > > On Oct 23, 12:32=A0pm, Mawa_fugo <cco...@netscape.net> wrote:
>
> > > > I have SP3 installed in the 10.1 - =A0but sometimes - once a while,=
 the
> > > > entire project just corrupted - when "rerun all" it TOOK the topmod=
ule
> > > > source from "nowhere" - nomatter how you change your topmodule it
> > > > still lock the topmodule source fom that mystery source
>
> > > > Oh my goodness
>
> > > The "Cleanup Project Files" under the "Project" menu can solve many o=
f
> > > these problems.
>
> > > kevin
>
> > Thanks for suggestion - it does something difference when I tried to
> > clean the project but it still lock the source from "nowhere"
>
> Hi
>
> I also had to deal with the same kind of issue with ISE 10.1SP3: after ch=
ecking out a project stored on a version control system (SVN), the top-leve=
l mark disappeared and the "Set as Top Module" action was disabled. =A0Need=
less to say that I tried all the usuals (amongst other things: "Cleanup Pro=
ject Files", "Check Syntax", removing/adding again the top-level source fil=
e) without much success.
>
> After a few minutes fiddling around, I tried to change the "Top-Level Sou=
rce Type" project property from HDL to EDIF and back to HDL --define long s=
hoot ;) -- and YGTBK! my top-level came back!
>
> > THis is a night mare
>
> At the very least it must scare some EEs away from FPGA design =A0;) =A0O=
ne a more serious note, I'm still hoping that five years after the buyout o=
f Hier Design, the people behind Planahead didn't get brainwashed and would=
 suggest the rest of the Design Software Division at Xilinx to put some com=
mon sense in ISE (such as using --again-- a text format for the project fil=
e).
>
> --
> Matthieu Michon <prenom....@gmail.com>- Hide quoted text -
>
> - Show quoted text -

11.x uses text format again

so at least once Xilinx has listened, well I bet they just had no
choice as the binary project file in their implementation is nothing
else and pure nightmare

Antti