Virtex 5 I/O

I have a pcb with a Virtex 5 and a programmable clock generator. I want to
use an LVDS clcok signal from the clock gen to the fpga. The problem is
that the clock generators default output is two 3.3V signals. The fpga bank
is connected to 1.8V. I would like to know if this will be a problem having
a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to be
LVDS output it should be ok but there is a brief period with the other
signals. 

Thanks

Jon	   
					
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This is likely to be a problem. Basically the protection diode on the
i/o cell will act as a short circuit to a 3.3V signal unless some
protection is added. Some details in http://www.xilinx.com/support/answers/=
10835.htm.

John Adair
Enterpoint Ltd. - Home of Raggedstone1. The PCI Development Board.

On 24 Oct, 18:53, "maxascent" <maxasc...@yahoo.co.uk> wrote:
> I have a pcb with a Virtex 5 and a programmable clock generator. I want t=
o
> use an LVDS clcok signal from the clock gen to the fpga. The problem is
> that the clock generators default output is two 3.3V signals. The fpga ba=
nk
> is connected to 1.8V. I would like to know if this will be a problem havi=
ng
> a 3.3V signal going to a 1.8V bank. Once I have programmed the clock to b=
e
> LVDS output it should be ok but there is a brief period with the other
> signals.
>
> Thanks
>
> Jon =A0 =A0 =A0 =A0
>
> --------------------------------------- =A0 =A0 =A0 =A0
> This message was sent using the comp.arch.fpga web interface onhttp://www=
.FPGARelated.com