Simple state machine output question

Andy wrote:

> To expand upon the timer/fsm example I posted a couple of weeks ago,
> you could have a timer procedure and an fsm procedure within a
> process, with local and "global" variables as desired. E.g. If the
> timer/timeout variables were declared before both procedures, then
> they could be read and manipulated by both, but if the state variable
> was declared within the FSM process, only FSM could read/manipulate
> the state.

I hear what you're saying.
If I had to put unrelated registers in the same entity,
I would do it like that.

I prefer to keep related registers together
and port map the wired interfaces to keep
the signal directions explicit.

> I have seen some of your examples illustrate the use of procedures in
> template processes, but I don't remember any specific to scope
> control.

I use port maps for scope control.

    -- Mike Treseler

Thanks for all the informative replies!
The book that I use as a VHDL reference does not go this deeply in the
subject of state machines, so I was a little lost.

I had a hunch that it was maybe not a good idea... as backhus'
response suggested, what I want are not latches, but registers to
store values from a few possible MUX'd input sources depending on the
state.. I should have been more clear on that.

And I think I may have been convinced to try the one clocked process
approach.. thankfully I was just finishing up the design of the states
and transitions, and haven't gotten too far into writing the code, so
I don't have to backtrack too much :)