Forums

XPLA3 coolrunner programming tool?

Started by Didi November 9, 2009
Some time ago I managed to get (under NDA) the programming info
from Xilinx so now I can program one of their coolrunners via JTAG
with my
toolchain (the CPLD on this design is reprogrammable over the net,
i.e. the
board CPU does its JTAG access etc.).

 I am now getting to what should be the easy part - writing the CPLD
source
to produce some (very simple) logic in a jedec file, after which I am
fine.

 I got the current xilinx software, started it under windows and got
really
scared.
 Last time I used a not-in-house written logic compiler tool it was
the PHDL
thing for the Philips coolrunner (before I had my tool working). It
was blindingly
obvious how to use it and I don't remember having to discover much if
anything
about it, I just used it. Did not waste an hour.

 I already wasted a few hours with the new xilinx tool.

 It looks like because I want to hit a nail - and I do know how to use
a hammer quite
well - I have to hire a farm of robots so one will drive another to
the shop
where they will pick a truck of hammers and bring them back for
another
robot to choose the right hammer, then they'l put together a table
onto
which the operation will be performed and eventrually the talk robot
will
be telling me how to proceed with which hammer so I can hit my nail
while
holding my arms to protect me from injuring myself.
Just terrific.

Can someone please suggest something simpler? Which is my fastest way?
I am not interested in learning all about their tools, I just want my
logic
into a jedec file (normally a 10 minutes' task here for what this is
with my
old coolrunner tools, but now I want to use a xcr3128xl part). There
is some
ABEL thing, is it usable in a way similar to more sane CPLD tools? (I
gather
it gets translated into vhdl to be processed but I guess I can live
with that for
now). Or their schematic entry, can it be usable? I wasted an hour
until I
**began to** figure out how to assign pins to things (far from having
mastered
that yet - not bad for a guy who has written his own toolchains for
such stuff
while having to do some reverse enginnering on the way, eh...).

Thanks,

Dimiter

------------------------------------------------------
Dimiter Popoff               Transgalactic Instruments

http://www.tgi-sci.com
------------------------------------------------------
http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/


On Nov 10, 3:14=A0am, Didi <d...@tgi-sci.com> wrote:
> Some time ago I managed to get (under NDA) the programming info > from Xilinx so now I can program one of their coolrunners via JTAG > with my > toolchain (the CPLD on this design is reprogrammable over the net, > i.e. the > board CPU does its JTAG access etc.). > > =A0I am now getting to what should be the easy part - writing the CPLD > source > to produce some (very simple) logic in a jedec file, after which I am > fine. > > =A0I got the current xilinx software, started it under windows and got > really > scared. > =A0Last time I used a not-in-house written logic compiler tool it was > the PHDL > thing for the Philips coolrunner (before I had my tool working). It > was blindingly > obvious how to use it and I don't remember having to discover much if > anything > about it, I just used it. Did not waste an hour. > > =A0I already wasted a few hours with the new xilinx tool. > > =A0It looks like because I want to hit a nail - and I do know how to use > a hammer quite > well - I have to hire a farm of robots so one will drive another to > the shop > where they will pick a truck of hammers and bring them back for > another > robot to choose the right hammer, then they'l put together a table > onto > which the operation will be performed and eventrually the talk robot > will > be telling me how to proceed with which hammer so I can hit my nail > while > holding my arms to protect me from injuring myself. > Just terrific. > > Can someone please suggest something simpler? Which is my fastest way? > I am not interested in learning all about their tools, I just want my > logic > into a jedec file (normally a 10 minutes' task here for what this is > with my > old coolrunner tools, but now I want to use a xcr3128xl part). There > is some > ABEL thing, is it usable in a way similar to more sane CPLD tools? (I > gather > it gets translated into vhdl to be processed but I guess I can live > with that for > now). Or their schematic entry, can it be usable? I wasted an hour > until I > **began to** figure out how to assign pins to things (far from having > mastered > that yet - not bad for a guy who has written his own toolchains for > such stuff > while having to do some reverse enginnering on the way, eh...). > > Thanks, > > Dimiter > > ------------------------------------------------------ > Dimiter Popoff =A0 =A0 =A0 =A0 =A0 =A0 =A0 Transgalactic Instruments > > http://www.tgi-sci.com > ------------------------------------------------------http://www.flickr.c=
om/photos/didi_tgi/sets/72157600228621276/ I wonder :) why so complicated.. JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it under NDA the jedec bitmap info is not so public, but i did RE it withing a few days :) as of "doing something" 1) use schematic for design entry 2) use the graphical tool to assign pins it works, you should get leds blinking withing hours from there go as want, use VHDL or verilog both work ok Antti
On Nov 10, 2:14=A0pm, Didi <d...@tgi-sci.com> wrote:
> There is some > ABEL thing, is it usable in a way similar to more sane CPLD tools? (I > gather it gets translated into vhdl to be processed but I guess I can li=
ve
> with that for now).
ABEL is a good tool flow for CPLD, and especially good if you want to keep close to the JED file. AFAIK, the Xilinx ABEL flow still works, and as you say, it converts into spagetti VHDL for the rest of the tool chains, and timing. Xilinx used to include some .abl source examples - if you search for .abl, what do you find ? The fitters can report (.rpt) Boolean Eqns in ABEL format, so you can correlate that with the source code, and track polarity fuses, and macrocell config fuses etc. Those report files also have some fuse-level matrix tables, that you can use to trace small changes. What happen in-between you can pretty much ignore :) Somewhere in the depths, I think the fitters still swallow PLA files/ BLIF formats, and if you are adept at tools, you could even create an assembler that output BLIF files for the fitters... A compact Xilinx CPLD flow would be nice to see :) -jg
In comp.arch.fpga Antti <antti.lukats@googlemail.com> wrote:

> JTAG info for Xilinx devices is PUBLIC (soso 95%) so no need to get it > under NDA
There are no 1532 BSDL files in the Xilinx/11.1/ISE/xpla3/data/ directory, so NDA is probably needed. ... -- Uwe Bonnes bon@elektron.ikp.physik.tu-darmstadt.de Institut fuer Kernphysik Schlossgartenstrasse 9 64289 Darmstadt --------- Tel. 06151 162516 -------- Fax. 06151 164321 ----------
On Nov 10, 8:59=A0am, -jg <jim.granvi...@gmail.com> wrote:

Hi Jim,
thanks for trying to help.
> ... > Xilinx used to include some .abl source examples - if you search for > .abl, what do you find ?
Nothing. This in what I downloaded from xilinx' site a month (or was it a few months) ago. It installed 4-5 separate things, all useless so far. Impact 11, ISE 11, Plan ahead 11, system generator 11, some accelDSP 11 thing. No .abl files to be seen. After a few hours of toying with the schematics tool I could not make it assign pins - just put a 74161 and wanted it to compile, no - it wants me to edit the vhdl file to finish, just does not work. Then I tried to start that "plan ahead" thing - just as useless, it offers me only FPGA choices. The rest of the applications appear to be stuff I won't ever need. I located a CD here I with their webpack 3.2 - it has survived somehow. It does get installed and there are 4 .abl files on it - the syntax looks sane enough. But (on the menus) I can see no way to make it generate a jedec file, this is probably done by the programmer part (the second icon it installed) which just does not work, pollutes the whole screen with "OK" windows in a loop (probably because it does not find its programmer). So I seem to be stuck - no Xilinx tool I have managed to locate so far will do Abel -> jedec. Paying them up to let me do that is not an option I would even consider. Can you please suggest something you have used and know it will work? Thanks, Dimiter ------------------------------------------------------ Dimiter Popoff Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
On Nov 11, 3:17=A0am, Didi <d...@tgi-sci.com> wrote:
> .... > So I seem to be stuck - no Xilinx tool I have managed to locate > so far will do Abel -> jedec. > ....
No longer that. I located on my disk something I had downloaded some months back while planning this effort - webpack 6.3i., on someones advice IIRC. It does seem to compile ABEL files, gets stuck at the end (with my source only) so far but this is after it generates the jedec file which is what I am after. Cannot see what it thinks it has done in the html report (it just does not work, "child process failed"), but well, this is a step in the right direction. But I am sure I will have to invest a few weeks into integrating the xpla3 into my logic compiler, these xilinx tools just are not usable. Here is a simple source for a 64 cell coolrunner from the Philips times: http://tgi-sci.com/misc/mb2ata.txt , I am used to be able to generate that within < a day... I will of course still welcome all help, I am still far from done with this. Dimiter ------------------------------------------------------ Dimiter Popoff =A0 =A0 =A0 =A0 =A0 =A0 =A0 Transgalactic Instruments http://www.tgi-sci.com ------------------------------------------------------ http://www.flickr.com/photos/didi_tgi/sets/72157600228621276/
On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote:
> > I will of course still welcome all help, I am still far from > done with this. > > Dimiter >
I have a handful of ABL files on a Xilinx stub here, I can compile those and zip the results if you give an email ? -jg
On Nov 11, 8:24=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > I will of course still welcome all help, I am still far from > > done with this. > > > Dimiter > > I have a handful of ABL files on a Xilinx stub here, I can compile > those and zip the results if you give an email ? > > -jg
Thanks Jim, I'll ask for that if I get stuck again. But for now I seem to be through, I managed to do some simplest code (1 toggling bit shifted through 5 others, just what I typed in without thinking) and lo and behold, this not only made it through the xilinx tool but got programmed into the part by my jedec->isp translator and my jtag thing... To my amazement the correct pins are toggling :-). Dimiter P.S. BTW, my email address here ( dp@tgi-sci.com ) is valid, in case you need it.
On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > I will of course still welcome all help, I am still far from > > done with this. > > > Dimiter > > I have a handful of ABL files on a Xilinx stub here, I can compile > those and zip the results if you give an email ? > > -jg
I've blown the dust off the directory(s), and it barfed on converting the old projects - but it happily made new ones. * new Project (name becomes subdir) * right click add source [select .ABL file] * double click on device, select XCR3128XL * click on source * Double click on Fitter report in process list * Double click on generate Jtag file in process list and voila, truckloads of files, but the ones that matter are .rpt, and .jed If I right-click on [fit].properties, I can select HDL equation style, where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses in the fitter report files. - select the most readable This is a legacy tool chain, but Xilinx can't have broken any of this, on newer versions can they ?! ;) -jg
On Nov 11, 9:46=A0am, -jg <jim.granvi...@gmail.com> wrote:
> On Nov 11, 7:24=A0pm, -jg <jim.granvi...@gmail.com> wrote: > > > On Nov 11, 5:43=A0pm, Didi <d...@tgi-sci.com> wrote: > > > > I will of course still welcome all help, I am still far from > > > done with this. > > > > Dimiter > > > I have a handful of ABL files on a Xilinx stub here, I can compile > > those and zip the results if you give an email ? > > > -jg > > I've blown the dust off the directory(s), and it barfed on converting > the old projects - but it happily made new ones. > * new Project =A0(name becomes subdir) > * right click add source [select .ABL file] > * double click on device, select XCR3128XL > * click on source > =A0 * Double click on Fitter report in process list > =A0 * Double click on =A0generate Jtag file in process list > > and voila, truckloads of files, but the ones that matter are .rpt, > and > .jed > > If I right-click on [fit].properties, I can select HDL equation style, > where you can choose Source/ABEL/Verilog/VHDL, and that's what it uses > in the fitter report files. - select the most readable > > This is a legacy tool chain, but Xilinx can't have broken any of this, > on newer versions can they ?! ;) > > -jg
sure they can break any legacy with any minor update of the tools they can Antti