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max. sinking current of XC95144xl cpld

Started by nishad November 12, 2009
My requirement is to replace fifteen 7 segment display drivers using cpld
logic.
Total I/O connected to display will be 15*8=120.
Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288XL
CPLD.
My doubt is that can the cpld sink 120 lines of 8mA simultaneously?


nishad,

Why do you doubt?  If the data sheet says an IO may sink 8 mA, then
why not ALL IO at 8 mA?

No problem.

The only concern here is ground/Vcc bounce:  yes, 128 * 8mA is a lot
of current, and you should make sure your pcb has good power and
ground planes, and the recommended bypass capacitors.

Austin
On Nov 12, 10:22=A0am, austin <aus...@xilinx.com> wrote:
> nishad, > > Why do you doubt? =A0If the data sheet says an IO may sink 8 mA, then > why not ALL IO at 8 mA? > > No problem. > > The only concern here is ground/Vcc bounce: =A0yes, 128 * 8mA is a lot > of current, and you should make sure your pcb has good power and > ground planes, and the recommended bypass capacitors. > > Austin
On the other hand if you really need 120 I/O's you may want to consider breaking it up into two packages. It might even save board area over one very large package. Of course that depends on how may additional pins you use to split the design in two. Sometimes it comes almost free, for example a two-wire serial bus. 1 Amp of switching current in a large PQFP results in lots of ground and Vcc bounce due to the large package lead inductance. Generally speaking, when using quad flat packs, the smaller the better because the die size of the chip inside gets closer to the overall package size as you get smaller, so the lead inductance is smaller, too. I'm not sure how it works with mature CPLD devices, but for FPGA's at least the price per I/O is better in smaller devices as well. Regards, Gabor
nishad wrote:
> My requirement is to replace fifteen 7 segment display drivers using cpld > logic. > Total I/O connected to display will be 15*8=120. > Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288XL > CPLD. > My doubt is that can the cpld sink 120 lines of 8mA simultaneously? > >
Do you actually NEED to drive them all with DC? Have you looked at multiplexing? One oddity of the eye's response is that the LEDs appear 90% as bright, even when only pulsed at 1/10th duty cycle. You can save a lot of pins, drive current, current limit resistors, etc. doing this. For 15 digits, you might use two sets of segment outputs, and have two digits illuminated at the same time. You would need either 8 or 15 digit select drivers, but those could be just SOT-23 P-channel FETs (or PNP transistors, but that requires a base resistor.) So, instead of 120 pins and 120 resistors, you go down to 16 resistors and 24 pins! If you don't have a lot of other logic in that CPLD, you can go down to a coolrunner in the 44 or 100-pin package. Jon
On Nov 13, 2:08=A0am, "nishad" <abnis...@gmail.com> wrote:
> My requirement is to replace fifteen 7 segment display drivers using cpld > logic. > Total I/O connected to display will be 15*8=3D120. > Each pin has to sink around 8mA, so Im planning to go for Xilinx XC95288X=
L
> CPLD. > My doubt is that can the cpld sink 120 lines of 8mA simultaneously?
A XC95288XLis an expensive shift register ? :) or is it doing other things as well ? LED drive is generally better done with smaller, daisy chained CPLDs, or even just shift registers. -jg
>nishad, > >Why do you doubt? If the data sheet says an IO may sink 8 mA, then >why not ALL IO at 8 mA? > >No problem. > >The only concern here is ground/Vcc bounce: yes, 128 * 8mA is a lot >of current, and you should make sure your pcb has good power and >ground planes, and the recommended bypass capacitors. > >Austin >
Thanks a lot for the reply... --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com