Interconnecting 3v3 LVDS transmitter to 2V5 Receiver

Hi.
Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..?
I am using cyclonII fpga for a receiver in which LVDS inputs are connected
to 2V5 powered bank.

will the FPGA be damaged with such interconnection..?
I am using these lines for clock (26MHz) interconnecting two boards
separated by a distance of 6 inches thru mother board.

Thank you in advance

sai

On 15 Nov., 14:37, "saijayram" <saijay...@gmail.com> wrote:
> Hi.
> Is there any harm in connecting 3V3 LVDS transmitter to 2V5 Receiver..?
> I am using cyclonII fpga for a receiver in which LVDS inputs are connected
> to 2V5 powered bank.
>
> will the FPGA be damaged with such interconnection..?
> I am using these lines for clock (26MHz) interconnecting two boards
> separated by a distance of 6 inches thru mother board.
>
> Thank you in advance
>
> sai

shouldn't be a problem, lvds is lvds regardless of what supply voltage
the reciever/transmitter is using

-Lasse

Sai,

LVDS is a standard.  The Vcco is immaterial (does not matter).

Yes, they are designed to interconnect (3.3 to 2.5, 2.5 to 3.3).

Austin