FPGA + Ethernet

Hello

I have to send and receive some data through ethernet, try to make a
transceiver. I found the LAN91C111 to save me from writing the part of
layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to
send and receive data with the integrated layer 2?. I'm new to fpga
and do not really know how to start this. thank you very much.

greetings

Potxoka <potxoka@gmail.com> writes:

>Hello

>I have to send and receive some data through ethernet, try to make a
>transceiver. I found the LAN91C111 to save me from writing the part of
>layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to
>send and receive data with the integrated layer 2?. I'm new to fpga
>and do not really know how to start this. thank you very much.

>greetings

	I'm just starting on a similar project (luckily for my own interest 
with no schedule or deadline :-)). I'm starting off with a Dragon board:

http://www.knjn.com/FPGA-PCI.html

which has a PHYless 10 megabit only implementation in VHDL source form as
part of the documentation (the connector with magnetics and a crystal was 
another $9 :-)). Once I've got my feet wet playing with that I have a 10/100 
PHY daughter card to add to the board to be able to do 10/100 with a real 
PHY (the only PHY daughter card I've found at a reasonable price :-))

http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html

and intend on using the ethernet open source MACs available from opencores.org.
It appears that 10/100/1000 PHYs run around $600 on daughter cards which will
make Gig somewhat exciting via DMA. It would probably be worthwhile to have 
a look at the opencores.org site in the RISC CPU area since I think some of
them have interfaces to the 10/100 MAC core which uses the wishbone bus and
that may help you alone. 
	The LAN91C111 looks to be a 10/100 integrated PHY/MAC with an ISA bus
type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn't be
all that hard, but then you are going to need an IP stack of some kind to 
actually get packets to it.
	If all you need to do is get some (non wire speed) packets on to the 
wire, you may be better off with one of the MCUs with built in ethernet such
as a PIC. They aren't fast enough to do wire speed but they will get packets
on the wire relatively easily although you are still going to need an IP stack
(as in Internet Protocol rather than Intellectual Property given the group
this is in :-)) to generate appropriate packets to give to the ethernet MAC. 

Peter Van Epp

On Nov 21, 4:32=A0am, van...@sfu.ca (Peter Van Epp) wrote:
> Potxoka <potx...@gmail.com> writes:
> >Hello
> >I have to send and receive some data through ethernet, try to make a
> >transceiver. I found the LAN91C111 to save me from writing the part of
> >layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to
> >send and receive data with the integrated layer 2?. I'm new to fpga
> >and do not really know how to start this. thank you very much.
> >greetings
>
> =A0 =A0 =A0 =A0 I'm just starting on a similar project (luckily for my ow=
n interest
> with no schedule or deadline :-)). I'm starting off with a Dragon board:
>
> http://www.knjn.com/FPGA-PCI.html
>
> which has a PHYless 10 megabit only implementation in VHDL source form as
> part of the documentation (the connector with magnetics and a crystal was
> another $9 :-)). Once I've got my feet wet playing with that I have a 10/=
100
> PHY daughter card to add to the board to be able to do 10/100 with a real
> PHY (the only PHY daughter card I've found at a reasonable price :-))
>
> http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html
>
> and intend on using the ethernet open source MACs available from opencore=
s.org.
> It appears that 10/100/1000 PHYs run around $600 on daughter cards which =
will
> make Gig somewhat exciting via DMA. It would probably be worthwhile to ha=
ve
> a look at the opencores.org site in the RISC CPU area since I think some =
of
> them have interfaces to the 10/100 MAC core which uses the wishbone bus a=
nd
> that may help you alone.
> =A0 =A0 =A0 =A0 The LAN91C111 looks to be a 10/100 integrated PHY/MAC wit=
h an ISA bus
> type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn't=
 be
> all that hard, but then you are going to need an IP stack of some kind to
> actually get packets to it.
> =A0 =A0 =A0 =A0 If all you need to do is get some (non wire speed) packet=
s on to the
> wire, you may be better off with one of the MCUs with built in ethernet s=
uch
> as a PIC. They aren't fast enough to do wire speed but they will get pack=
ets
> on the wire relatively easily although you are still going to need an IP =
stack
> (as in Internet Protocol rather than Intellectual Property given the grou=
p
> this is in :-)) to generate appropriate packets to give to the ethernet M=
AC.
>
> Peter Van Epp

hi,

I had already looked into OpenCores, the problem is that I=B4m newbie to
fpga and more in vhdl / verilog, so as not to implement it properly.
why LAN91C111 had thought of that I avoid having to implement the mac.
IP stack do not need, since the only need that I have to send and
receive packets in a layer 2 (mac), but being a rookie, also going to
cost me to use this phy from the fpga ;-). so wondered if anyone had
already implemented this.

National PHY have sent me some samples and is relatively cheap (5
dollars to 16 dollars of LAN91C111, ufff). My main idea was to have
used these for this purpose and implement the mac on the fpga, but I
think I would be very difficult. I have also seen some phy (National)
with pci connection, but a PCI attack from an FPGA must not be easy
(apart from implementing the mac ;-P ), right?. Thanks

Greetings

On 21 nov, 14:23, Potxoka <potx...@gmail.com> wrote:
> On Nov 21, 4:32=A0am, van...@sfu.ca (Peter Van Epp) wrote:
>
>
>
> > Potxoka <potx...@gmail.com> writes:
> > >Hello
> > >I have to send and receive some data through ethernet, try to make a
> > >transceiver. I found the LAN91C111 to save me from writing the part of
> > >layer 2 (MAC). Does anyone have any example in VHDL or Verilog how to
> > >send and receive data with the integrated layer 2?. I'm new to fpga
> > >and do not really know how to start this. thank you very much.
> > >greetings
>
> > =A0 =A0 =A0 =A0 I'm just starting on a similar project (luckily for my =
own interest
> > with no schedule or deadline :-)). I'm starting off with a Dragon board=
:
>
> >http://www.knjn.com/FPGA-PCI.html
>
> > which has a PHYless 10 megabit only implementation in VHDL source form =
as
> > part of the documentation (the connector with magnetics and a crystal w=
as
> > another $9 :-)). Once I've got my feet wet playing with that I have a 1=
0/100
> > PHY daughter card to add to the board to be able to do 10/100 with a re=
al
> > PHY (the only PHY daughter card I've found at a reasonable price :-))
>
> >http://www.enterpoint.co.uk/moelbryn/modules/ethernet_phy.html
>
> > and intend on using the ethernet open source MACs available from openco=
res.org.
> > It appears that 10/100/1000 PHYs run around $600 on daughter cards whic=
h will
> > make Gig somewhat exciting via DMA. It would probably be worthwhile to =
have
> > a look at the opencores.org site in the RISC CPU area since I think som=
e of
> > them have interfaces to the 10/100 MAC core which uses the wishbone bus=
 and
> > that may help you alone.
> > =A0 =A0 =A0 =A0 The LAN91C111 looks to be a 10/100 integrated PHY/MAC w=
ith an ISA bus
> > type (i.e. not PCI) bus interface. Interfacing that to the FPGA shouldn=
't be
> > all that hard, but then you are going to need an IP stack of some kind =
to
> > actually get packets to it.
> > =A0 =A0 =A0 =A0 If all you need to do is get some (non wire speed) pack=
ets on to the
> > wire, you may be better off with one of the MCUs with built in ethernet=
 such
> > as a PIC. They aren't fast enough to do wire speed but they will get pa=
ckets
> > on the wire relatively easily although you are still going to need an I=
P stack
> > (as in Internet Protocol rather than Intellectual Property given the gr=
oup
> > this is in :-)) to generate appropriate packets to give to the ethernet=
 MAC.
>
> > Peter Van Epp
>
> hi,
>
> I had already looked into OpenCores, the problem is that I=B4m newbie to
> fpga and more in vhdl / verilog, so as not to implement it properly.
> why LAN91C111 had thought of that I avoid having to implement the mac.
> IP stack do not need, since the only need that I have to send and
> receive packets in a layer 2 (mac), but being a rookie, also going to
> cost me to use this phy from the fpga ;-). so wondered if anyone had
> already implemented this.
>
> National PHY have sent me some samples and is relatively cheap (5
> dollars to 16 dollars of LAN91C111, ufff). My main idea was to have
> used these for this purpose and implement the mac on the fpga, but I
> think I would be very difficult. I have also seen some phy (National)
> with pci connection, but a PCI attack from an FPGA must not be easy
> (apart from implementing the mac ;-P ), right?. Thanks
>
> Greetings

Sorry, lan91c111 25 dolars.

Potxoka <potxoka@gmail.com> writes:

<snip>
>hi,

>I had already looked into OpenCores, the problem is that I=B4m newbie to
>fpga and more in vhdl / verilog, so as not to implement it properly.
>why LAN91C111 had thought of that I avoid having to implement the mac.
>IP stack do not need, since the only need that I have to send and
>receive packets in a layer 2 (mac), but being a rookie, also going to
>cost me to use this phy from the fpga ;-). so wondered if anyone had
>already implemented this.

>National PHY have sent me some samples and is relatively cheap (5
>dollars to 16 dollars of LAN91C111, ufff). My main idea was to have
>used these for this purpose and implement the mac on the fpga, but I
>think I would be very difficult. I have also seen some phy (National)
>with pci connection, but a PCI attack from an FPGA must not be easy
>(apart from implementing the mac ;-P ), right?. Thanks

>Greetings

	I think you are going to find you need an IP stack. At the very least
you are going to need to implement arp to find the MAC address of whoever
you want to communicate with and perhaps DHCP to get an IP address for your
device (although you could hardcode both although it won't be too flexable). 
Then you will need to format UDP packets with appropriate headers, data and 
crc to send to the MAC address you found via arp.  A TCP connection is much 
more complex.  A PHY/MAC combination will only get packets (with appropriate 
content from somewhere, usually the IP stack :-)), on the wire. You may want 
to look at something like the PIC18F66J60-I which is around $6 at Digikey. It 
has a 10 meg phy and Mac on board and I think there is an IP library available 
from Microchip. Your FPGA would send the data to the PIC which would then 
run it through the IP stack and send it as appropriate. I expect you are correct
that getting one of the opencores MACs to work isn't easy (I haven't gotten
that far yet so I can't say for sure :-)). Depending on your time line and
budget you may be best to start with the Dragon board I mentioned as it comes
with do it your self VHDL to do 10 meg (no PHY) ethernet and a PCI interface
(the Dragon is $299 US + as noted $9 for the ether connector and oscillator)
that may be your best bet to learn more about ethernet and fpgas. Good luck!

Peter Van Epp

On Sat, 21 Nov 2009 19:44:49 +0000, Peter Van Epp wrote:

> 	I think you are going to find you need an IP stack. At the very least
> you are going to need to implement arp to find the MAC address of whoever
> you want to communicate with and perhaps DHCP to get an IP address for your
> device (although you could hardcode both although it won't be too flexable). 
> Then you will need to format UDP packets with appropriate headers, data and 
> crc to send to the MAC address you found via arp.  A TCP connection is much 
> more complex.  A PHY/MAC combination will only get packets (with appropriate 
> content from somewhere, usually the IP stack :-)), on the wire. 

Sending raw ethernet packets may be good enough for some applications. If
you have a private network, and use some dedicated software on an attached
PC, you can define your own protocol using ethernet packets.

I've used such a method for a tiny bootloader that could boot over
ethernet, using proprietary packet format, and a special boot server
program running on a PC. 

Of course, if the device needs to talk to existing IP-family protocols,
some more code is required, although it's possible to cut some corners
too. For instance, if the device is passive, you can skip ARP, and just
reverse the src/dst MAC address to turn a request into a response. 

Peter Van Epp wrote:
> Depending on your time line and
> budget you may be best to start with the Dragon board I mentioned as it comes
> with do it your self VHDL to do 10 meg (no PHY) ethernet and a PCI interface
> (the Dragon is $299 US + as noted $9 for the ether connector and oscillator)
> that may be your best bet to learn more about ethernet and fpgas. Good luck!

If money is an issue but not time or bandwidth, I suggest buying
a ready-made module based on the ENC28J60. I have found (and bought)
several on eBay, they are _cheap_ and _small_ . Mine are marked
as coming from http://www.the0.net

BTW the interface is synchronous serial (SPI) up to 20MHz (so it's only 10BasetT)
but it is easier to start using Ethernet with the HW/MAC/PHT already designed.
And later it can be integrated in a product, due to the size and price.

just .2$,

> Peter Van Epp
yg

-- 
http://ygdes.com / http://yasep.org

whygee wrote:
> If money is an issue but not time or bandwidth, I suggest buying
> a ready-made module based on the ENC28J60. I have found (and bought)
> several on eBay, they are _cheap_ and _small_ . Mine are marked
> as coming from http://www.the0.net

I've found the store's address again :
http://cgi.ebay.com/ws/eBayISAPI.dll?ViewItem&item=300368473658
the cost is about $17, +$7 for shipping.
If someone finds even cheaper, please tell me.
At least it's cheaper and smaller than Microchip's own modules.

OK, it's not 100BaseT but the serial interface requires much
less pins than the original poster's solution.
I have also found several step-by-step introductions
to this chips on the 'net. Though I have not yet had
the time to try the module.

yg
-- 
http://ygdes.com / http://yasep.org