Forums

Reading Altera datasheets

Started by Simon November 20, 2009
I'm trying to implement an SDRAM controller for the Altera EP2C8 on a
TS-7300 board (from http://www.embeddedarm.com), and I found a
document from Altera (http://www.pldworld.net/_altera/html/_excalibur/
nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in
calculating how the PLL ought to be set up.

The problem I'm facing is that the datasheet (http://www.altera.com/
literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to
have the information needed by the calculations in the tuning guide.
The tuning guide is referencing a table ("table 4:36. EP1C20 Column
pin global clock external i/o timing parameters) that shows t_su,
s_inh, and t_outco for a Cyclone 1, and the closest table I can find
in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and
t_pllcout (table 5-23 :  EP2C8/A Column pins global clock timing
parameters). These don't appear to be the same thing :)

Can anyone point me in the right direction ? Much appreciated if you
do :)

Cheers,
   Simon
On Nov 20, 1:31=A0pm, Simon <goo...@gornall.net> wrote:
> I'm trying to implement an SDRAM controller for the Altera EP2C8 on a > TS-7300 board (fromhttp://www.embeddedarm.com), and I found a > document from Altera (http://www.pldworld.net/_altera/html/_excalibur/ > nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in > calculating how the PLL ought to be set up. > > The problem I'm facing is that the datasheet (http://www.altera.com/ > literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to > have the information needed by the calculations in the tuning guide. > The tuning guide is referencing a table ("table 4:36. EP1C20 Column > pin global clock external i/o timing parameters) that shows t_su, > s_inh, and t_outco for a Cyclone 1, and the closest table I can find > in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and > t_pllcout (table 5-23 : =A0EP2C8/A Column pins global clock timing > parameters). These don't appear to be the same thing :) > > Can anyone point me in the right direction ? Much appreciated if you > do :) > > Cheers, > =A0 =A0Simon
No-one got any hints ? Cheers, Simon.
Simon wrote:
> On Nov 20, 1:31 pm, Simon <goo...@gornall.net> wrote: >> I'm trying to implement an SDRAM controller for the Altera EP2C8 on a >> TS-7300 board (fromhttp://www.embeddedarm.com), and I found a >> document from Altera (http://www.pldworld.net/_altera/html/_excalibur/ >> nios-sdram-tuning/SDRAM_PLL_Tuning.pdf) which looks helpful in >> calculating how the PLL ought to be set up. >> >> The problem I'm facing is that the datasheet (http://www.altera.com/ >> literature/hb/cyc2/cyc2_cii5v1_01.pdf) for the EP2C8 doesn't seem to >> have the information needed by the calculations in the tuning guide. >> The tuning guide is referencing a table ("table 4:36. EP1C20 Column >> pin global clock external i/o timing parameters) that shows t_su, >> s_inh, and t_outco for a Cyclone 1, and the closest table I can find >> in the datasheet for the cyclone 2 has t_cin, t_cout, t_pllcin, and >> t_pllcout (table 5-23 : EP2C8/A Column pins global clock timing >> parameters). These don't appear to be the same thing :) >> >> Can anyone point me in the right direction ? Much appreciated if you >> do :) >> >> Cheers, >> Simon > > No-one got any hints ?
Haven't done it with a Cyclone, but with a Stratix, you get these numbers from the timing output after a build. Make your calculations and substitute into the PLL and build again. Mark