hello, I woud like to design a 32,768 Hz stable input for calibrated real-time operation of a FPGA-centric system, as power-of-two frequencies make digital computations very easy, using shifts instead of divides for motion equations. * I "could" use a multiple of this frequency as my main clock but I find no suitable canned oscillator (a 3.3V 5x7mm one is preferred, cheaper is better) examples : - 18.423MHz / 32768 = 562.5 => almost there... so I would have to divide it by 5*5*5*3*3 to get a power-of-two frequency, but only 16KHz. - 24.576MHz (close to my target 25MHz) = 2*3*5*5*5 * 32768 so I get a nice 65536Hz after 4 small prescalers but my other 25MHz circuits won't be happy by 1.7%. And I have already bought the 25MHz oscillators :-/ * I "could" make a custom oscillator with a cheap&tiny "wristwatch" cristal but the power consumption, stability and acuracy would not be optimised. * My target is the Actel A3P250 in TQFP100 package. I "could" use his Fusion sibling (that has an integrated and separately powered RTC oscillator) but the price difference is ... not enchanting. And the package is different. And I have the A3P250 already :-/ * I "could" use a common external I2C clock/calendar but i'd prefer SPI and the cheap chips don't (rarely ?) provide the 32KHz output (that I reuse to sequence stuff). So... what's left ? yg -- http://ygdes.com / http://yasep.org
32KHz RTC for FPGA
Started by ●November 25, 2009
Reply by ●November 25, 20092009-11-25
On Nov 26, 9:22=A0am, whygee <y...@yg.yg> wrote:> > So... what's left ?It's not clear exactly what you are asking ? Epson, EM Microelectronic et al, have 32Khz osc modules, that include the crystal. Maxim have one that is TCXO as well, and if precision matters, then you will need txco. NXP PCF2129 is another candidate, but less stocked. MicroCrystal.com also have a range. Some tcxo's are fixes in time, not frequency, so watch the details ;) -jg
Reply by ●November 25, 20092009-11-25
On Nov 25, 3:22=A0pm, whygee <y...@yg.yg> wrote:> hello, > > I woud like to design a 32,768 Hz stable input for > calibrated real-time operation of a FPGA-centric system, > as power-of-two frequencies make digital computations > very easy, using shifts instead of divides for motion equations. > > =A0 * I "could" use a multiple of this frequency as my > main clock but I find no suitable canned oscillator > (a 3.3V 5x7mm one is preferred, cheaper is better) > > examples : > =A0 - 18.423MHz / 32768 =3D 562.5 =3D> almost there... > =A0 so I would have to divide it by 5*5*5*3*3 > =A0 =A0to get a power-of-two frequency, but only 16KHz. > =A0 - 24.576MHz (close to my target 25MHz) =3D 2*3*5*5*5 * 32768 > =A0 =A0so I get a nice 65536Hz after 4 small prescalers > =A0 =A0but my other 25MHz circuits won't be happy by 1.7%. > And I have already bought the 25MHz oscillators :-/ > > =A0 * I "could" make a custom oscillator with a cheap&tiny "wristwatch" > cristal but the power consumption, stability and acuracy > would not be optimised. > > =A0 * My target is the Actel A3P250 in TQFP100 package. > I "could" use his Fusion sibling (that has an integrated > and separately powered RTC oscillator) but the price > difference is ... not enchanting. And the package is different. > And I have the A3P250 already :-/ > > =A0 * I "could" use a common external I2C clock/calendar > but i'd prefer SPI and the cheap chips don't (rarely ?) provide > the 32KHz output (that I reuse to sequence stuff). > > So... what's left ? > > yg > --http://ygdes.com/http://yasep.orgI think you've covered all the bases given your apparently conflicting requirements. Often engineering is a matter of determining an optimal combination of all requirements, but sometimes it is a matter of trading off one against the other so that neither is optimal, but both are adequate. So if you *must* use 25 MHz, then you need a 25 MHz oscillator, not 24.576. That means you have to provide another clock. If using a 32.576 kHz oscillator is too power consuming, how do you expect to get this second clock? I don't see how a clock chip would be any better than a 32.576 kHz oscillator. The clock chip still uses a crystal. Rick
Reply by ●November 25, 20092009-11-25
On Nov 26, 9:22=A0am, whygee <y...@yg.yg> wrote:> hello, > > I would like to design a 32,768 Hz stable input<snip>> And I have already bought the 25MHz oscillators :-/ > > So... what's left ?A different approach... How stable ? - If you have 25Mhz Osc, then divide by 762/763 in a ratio basis, gets you to within 5.2ppm of 32.768 on average, and gives just 40ns of period jitter. Tolerable? 1-((2*(762/25e6)+29*(763/25e6))/31)*32768 ans =3D 5.20258064516129032e-6 Is your 25MHz better than 5ppm ;) -jg
Reply by ●November 25, 20092009-11-25
On Nov 26, 9:22=A0am, whygee <y...@yg.yg> wrote:> hello, > > I woud like to design a 32,768 Hz stable input for > calibrated real-time operation of a FPGA-centric system, > as power-of-two frequencies make digital computations > very easy, using shifts instead of divides for motion equations.If this is for motion control, it's likely the 40ns jitter and 5ppm of my earlier example is fine... .. but in case it is not, if you are going to x4 the 25MHz anyway in a PLL, then this can apply : 1-((1*(3051/100e6)+3*(3052/100e6))/4)*32768 ans =3D 2.56e-6 ie from 100MHz, you get 2.56ppm, and 10ns jitter, and any binary time under 32768/4, has no jitter at all. -jg
Reply by ●November 26, 20092009-11-26
-jg wrote:> There are other solutions: > > My original one, from 25Mhz, has a 31 modulo > swallow : with /762 /763 counter > 1-((2*(762/25e6)+29*(763/25e6))/31)*32768 > ans = 5.20258064516129032e-6 > > and there is a solution at 50MHz > 1-((1*(1525/50e6)+7*(1526/50e6))/8)*32768 > ans = 2.56e-6is the barrell of aspirine also provided ? :-)> - interesting this is also 2.56ppm, but with > a modulo 8 swallow. > Can you get a 11 bit preloadable counter, at 50Mhz ?it should do, but that's looking overengineered :-/> Or, this can be done as fixed /25; /61, and a single width CE pulse, > to swallow one clock, to get /1526a proper crystal frequency sounds better :-/>> The only effect is on ego (or marketing) because 100MHz is a "sweet spot" >> and 98 looks more like a miss, even though static timing analysis >> reports better than that. But who said that marketing was compatible >> with engineering ? > Marketing would call a 98Mhz point a "100Mhz system" anyway ;)My CPU is memory-synchronous so it is limited by the external asynch SRAM's speed anyway... The fastest ones I could find are 8ns so I'm not sure that a 10ns cycle is realistic. I have synchronous RAMs that are faster but they introduce delays... ... I just looked at the datasheets and the ENC28J60 provides a "clock out" that is configured as 25/4=6.25MHz after power-on reset. This pin is also available on the module's output \o/ I looked further and Microchip was careful : the oscillator is not disabled when the chip sleeps, only when the clock control register is set so. So no dirty business with getting around stupid system interlocks during sleep :-) I could switch the integrated CPU clock source to the 25MHz when booted. However, the 10BasetT module is optional, and I have only one PLL so frequency multiplication is possible on only one main clock... The question of price is very important : I could get a bunch of suitable crystals for a good price, but canned oscillators are not as available, and not for the desired frequency. So I'm looking at how I can safely drive the crystal without adding too many analog parts. In fact, a cheap PIC12F could do the trick and the remaining pins could replace the voltage supervisors. The space eaten by the HC49S can is compensated by some removed SOT23s ... The price of the crystal + cheap PIC is lower than a smaller oscillator :-/> -jgyg -- http://ygdes.com / http://yasep.org
Reply by ●November 26, 20092009-11-26
-jg wrote:> A 9 bit, 16Mhz counter should be viable ?did anyone tell you that you're obsessed ? :-D> -jgyg -- http://ygdes.com / http://yasep.org
Reply by ●November 26, 20092009-11-26
-jg wrote:> I thought 'standard values' and price were important?I go for 12.288MHz as main clock, I can divide easily by simple integers to get RS232, 32.768KHz and some audio frequencies. I can also PLL up to 98MHz wich is close enough to 100MHz. I can reuse the 25MHz oscillators later. I'm now looking around for better deals than the usual/mainstream distributors. I have found crystals but driving them properly opens a new can of worms... like price, surface, complexity, calibration...> -jgyg -- http://ygdes.com / http://yasep.org
Reply by ●November 26, 20092009-11-26
On Nov 26, 6:25=A0pm, whygee <y...@yg.yg> wrote:> > Can you get a 11 bit preloadable counter, at 50Mhz ? > > it should do, but that's looking overengineered :-/ > > > Or, this can be done as fixed /25; /61, and a single width CE pulse, > > to swallow one clock, to get /1526 > > a proper crystal frequency sounds better :-/? but a lot more expensive, than < 20FF in a FPGA. I thought 'standard values' and price were important? -jg
Reply by ●November 26, 20092009-11-26
On Nov 26, 8:51=A0am, whygee <y...@yg.yg> wrote:> -jg wrote: > > I thought 'standard values' and price were important? > > I go for 12.288MHz as main clock, > I can divide easily by simple integers to get RS232, 32.768KHz > and some audio frequencies. I can also PLL up to 98MHz wich > is close enough to 100MHz. I can reuse the 25MHz oscillators later. > > I'm now looking around for better deals > than the usual/mainstream distributors. > I have found crystals but driving them > properly opens a new can of worms... > like price, surface, complexity, calibration... > > > -jg > > yg > > --http://ygdes.com/http://yasep.orgyou cant get it all. getting GOOD smd oscillators at 0.50$ at low qty in A3P250 you do have the PLL for free but it has its lower frequency so if you use 32khz you cant use the PLL and can not have any frequency highere then 32KHz at all, unless you run own ring- oscillator with dynamic calibration Antti
