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what is Timing generating before interfacing?

Started by Joshi & Joshi December 15, 2009
Hi ..

'm having ADC chip "ADS 8364"  wit 25m Hz input Clock . ADC output
Signal Going to FPGA and its out signal going to processor fr further
process.

my problem is before writing vhdl Code i want generate timings ADC to
FPGA but

(1) i don no what is this timing generation ?

(2) why this necessary before Code ?

(3)Can any one give example timing code generation for ADC's

Waiting for all yur Inputs

Joshi


On Dec 15, 1:24=A0am, "Joshi & Joshi" <joship...@gmail.com> wrote:
> Hi .. > > 'm having ADC chip "ADS 8364" =A0wit 25m Hz input Clock . ADC output > Signal Going to FPGA and its out signal going to processor fr further > process. > > my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? >
A timing diagram. Refer to the data sheet for the part.
> (2) why this necessary before Code ? >
It isn't.
> (3)Can any one give example timing code generation for ADC's >
http://focus.ti.com/lit/ds/symlink/ads8364.pdf (Page 26) KJ
On Dec 15, 7:09=A0am, KJ <kkjenni...@sbcglobal.net> wrote:

> > http://focus.ti.com/lit/ds/symlink/ads8364.pdf(Page 26) >
Make that page 6, not 26 KJ
>On Dec 15, 7:09=A0am, KJ <kkjenni...@sbcglobal.net> wrote: > >> >> http://focus.ti.com/lit/ds/symlink/ads8364.pdf(Page 26) >> >Make that page 6, not 26 > >KJ >
thanks fr Input ya i had this Data sheet .. But i want Know how to make use use of Giving timing diagrams in VHDL Code .. Can any one Give Give Xmple Code fr Timing Generating Code .. for what purpose we want generate this Code? Joshi --------------------------------------- This message was sent using the comp.arch.fpga web interface on http://www.FPGARelated.com
On Mon, 14 Dec 2009 22:24:40 -0800 (PST)
"Joshi & Joshi" <joshiplns@gmail.com> wrote:

> Hi .. > > 'm having ADC chip "ADS 8364" wit 25m Hz input Clock . ADC output > Signal Going to FPGA and its out signal going to processor fr further > process. > > my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? > > (2) why this necessary before Code ? > > (3)Can any one give example timing code generation for ADC's > > Waiting for all yur Inputs > > Joshi > >
You generate timed sequences of events by writing a finite state machine clocked by a system clock of known frequency. -- Rob Gaddi, Highland Technology Email address is currently out of order
On 15 Dez., 07:24, "Joshi & Joshi" <joship...@gmail.com> wrote:
> my problem is before writing vhdl Code i want generate timings ADC to > FPGA but > > (1) i don no what is this timing generation ? > (2) why this necessary before Code ?
We also don't know. I find it really hard from your post to understand what it is that you need. Maybe you are talking about a testbench that when run in a simulator creates the waveforms that you see in the data sheet so that you can see whether your hdl code reacts correctly to them? In this case you can do stuff like this: wait for 10ns; cs <= '1'; wait for 5ms; .... Kolja Sulimma