Hello, I need to implement a project as a part of my Masters curriculum using fpga devices that would generate delays, that is generate higher output frequencies than the system clock using propagation delays. I'm using ISE tool for the same. I'm new to this technology and would really appreciate if i could get some help on this. Thanks in advance. --------------------------------------- Posted through http://www.FPGARelated.com
timing properties of fpga devices at sub-clock frequencies
Started by ●January 25, 2010
Reply by ●January 25, 20102010-01-25
On Jan 25, 6:25=A0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:> Hello, > > I need to implement a project as a part of my Masters curriculum using fp=ga> devices that would generate delays, that is generate higher output > frequencies than the system clock using propagation delays. I'm using ISE > tool for the same. I'm new to this technology and would really appreciate > if i could get some help on this. Thanks in advance. > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comThis is a somewhat confused question ? If you want to generate delays, you do not need to 'over-clock' - just choose a FPGA with inbuilt delay blocks, and they will have a step size, much smaller than any clock precision. ie the FPGA vendors have solved this problem already. -jg
Reply by ●January 25, 20102010-01-25
>On Jan 25, 6:25=A0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> >wrote: >> Hello, >> >> I need to implement a project as a part of my Masters curriculum usingfp=>ga >> devices that would generate delays, that is generate higher output >> frequencies than the system clock using propagation delays. I'm usingISE>> tool for the same. I'm new to this technology and would reallyappreciate>> if i could get some help on this. Thanks in advance. >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >This is a somewhat confused question ? >If you want to generate delays, you do not need to 'over-clock' - just >choose a FPGA with inbuilt delay blocks, and they will have a step >size, much smaller than any clock precision. >ie the FPGA vendors have solved this problem already. > >-jg >Thanks for ur response. As I'm new to this technology I really dont understand the terminologies used. I dont need to do h/w implementation, just a simulation would be enough. Also i need to do physical implementations(dont know what that means).> >--------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●January 25, 20102010-01-25
On Jan 25, 10:17=A0am, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:> >On Jan 25, 6:25=3DA0pm, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com= > > >wrote: > >> Hello, > > >> I need to implement a project as a part of my Masters curriculum using > fp=3D > >ga > >> devices that would generate delays, that is generate higher output > >> frequencies than the system clock using propagation delays. I'm using > ISE > >> tool for the same. I'm new to this technology and would really > appreciate > >> if i could get some help on this. Thanks in advance. > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >This is a somewhat confused question ? > >If you want to generate delays, you do not need to 'over-clock' - just > >choose a FPGA with inbuilt delay blocks, and they will have a step > >size, much smaller than any clock precision. > >ie the FPGA vendors have solved this problem already. > > >-jg > > Thanks for ur response. As I'm new to this technology I really dont > understand the terminologies used. I dont need to do h/w implementation, > just a simulation would be enough. Also i need to do physical > implementations(dont know what that means). > > > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comIf you need to do physical implementations, you need to do hardware implementations. If you're doing more than just using the high speed interface (such as the Rocket I/O used in the Xilinx chips you can target with ISE) to deliver delay granularity of about 1/3 of a nanosecond, you will have difficulty getting a good simulation since proper timing situation is difficult. If you're looking to push the delay granularity, there are techniques which can be used to leverage internal delays within CLBs or carry chains that don't lend themselves to exceptional timing simulation. If you're clear on what you want to accomplish we may be able to provide some good direction or point you to application notes on existing designs. But you *really* need to know what's expected of you in the way of the physical implementation requested. - John_H
Reply by ●January 26, 20102010-01-26
>On Jan 25, 10:17=A0am, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> >wrote: >> >On Jan 25, 6:25=3DA0pm, "Pallavi"<pallavi_mp@n_o_s_p_a_m.rediffmail.com=>> >> >wrote: >> >> Hello, >> >> >> I need to implement a project as a part of my Masters curriculumusing>> fp=3D >> >ga >> >> devices that would generate delays, that is generate higher output >> >> frequencies than the system clock using propagation delays. I'musing>> ISE >> >> tool for the same. I'm new to this technology and would really >> appreciate >> >> if i could get some help on this. Thanks in advance. >> >> >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 >> >> Posted throughhttp://www.FPGARelated.com >> >> >This is a somewhat confused question ? >> >If you want to generate delays, you do not need to 'over-clock' - just >> >choose a FPGA with inbuilt delay blocks, and they will have a step >> >size, much smaller than any clock precision. >> >ie the FPGA vendors have solved this problem already. >> >> >-jg >> >> Thanks for ur response. As I'm new to this technology I really dont >> understand the terminologies used. I dont need to do h/wimplementation,>> just a simulation would be enough. Also i need to do physical >> implementations(dont know what that means). >> >> >> >> --------------------------------------- =A0 =A0 =A0 =A0 >> Posted throughhttp://www.FPGARelated.com > >If you need to do physical implementations, you need to do hardware >implementations. > >If you're doing more than just using the high speed interface (such as >the Rocket I/O used in the Xilinx chips you can target with ISE) to >deliver delay granularity of about 1/3 of a nanosecond, you will have >difficulty getting a good simulation since proper timing situation is >difficult. > >If you're looking to push the delay granularity, there are techniques >which can be used to leverage internal delays within CLBs or carry >chains that don't lend themselves to exceptional timing simulation. > >If you're clear on what you want to accomplish we may be able to >provide some good direction or point you to application notes on >existing designs. > >But you *really* need to know what's expected of you in the way of the >physical implementation requested. > >- John_H >Hi, John, Can I use gates(adder,AND gate,etc.) to generate delays. If yes what should be the input and output. I'm just supposed to do simulation, no physical implementation required. If would be really helpful if I could get some help on this. Thanks. --------------------------------------- Posted through http://www.FPGARelated.com
Reply by ●January 26, 20102010-01-26
On Jan 26, 10:54=A0am, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:> >On Jan 25, 10:17=3DA0am, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.co=m>> >wrote: > >> >On Jan 25, 6:25=3D3DA0pm, "Pallavi" > > <pallavi_mp@n_o_s_p_a_m.rediffmail.com=3D > > > > >> >wrote: > >> >> Hello, > > >> >> I need to implement a project as a part of my Masters curriculum > using > >> fp=3D3D > >> >ga > >> >> devices that would generate delays, that is generate higher output > >> >> frequencies than the system clock using propagation delays. I'm > using > >> ISE > >> >> tool for the same. I'm new to this technology and would really > >> appreciate > >> >> if i could get some help on this. Thanks in advance. > > >> >> --------------------------------------- =3D3DA0 =3D3DA0 =3D3DA0 =3D=3DA0> >> >> Posted throughhttp://www.FPGARelated.com > > >> >This is a somewhat confused question ? > >> >If you want to generate delays, you do not need to 'over-clock' - jus=t> >> >choose a FPGA with inbuilt delay blocks, and they will have a step > >> >size, much smaller than any clock precision. > >> >ie the FPGA vendors have solved this problem already. > > >> >-jg > > >> Thanks for ur response. As I'm new to this technology I really dont > >> understand the terminologies used. I dont need to do h/w > implementation, > >> just a simulation would be enough. Also i need to do physical > >> implementations(dont know what that means). > > >> --------------------------------------- =3DA0 =3DA0 =3DA0 =3DA0 > >> Posted throughhttp://www.FPGARelated.com > > >If you need to do physical implementations, you need to do hardware > >implementations. > > >If you're doing more than just using the high speed interface (such as > >the Rocket I/O used in the Xilinx chips you can target with ISE) to > >deliver delay granularity of about 1/3 of a nanosecond, you will have > >difficulty getting a good simulation since proper timing situation is > >difficult. > > >If you're looking to push the delay granularity, there are techniques > >which can be used to leverage internal delays within CLBs or carry > >chains that don't lend themselves to exceptional timing simulation. > > >If you're clear on what you want to accomplish we may be able to > >provide some good direction or point you to application notes on > >existing designs. > > >But you *really* need to know what's expected of you in the way of the > >physical implementation requested. > > >- John_H > > Hi, John, > > Can I use gates(adder,AND gate,etc.) to generate delays. If yes what shou=ld> be the input and output. I'm just supposed to do simulation, no physical > implementation required. If would be really helpful if I could get some > help on this. Thanks. =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comIt would really help to study the logic block architecture of your FPGA if you want to do "gate-level" delays. Usually Adders, AND gates, etc. are implemented in LUT's and possibly some dedicated carry logic. If you want to create delays and not have the synthesis tools rip out your delay as a piece of unnecessary logic, you need to instantiate a LUT or carry element to create your delay. I believe that there are app notes on the Xilinx website for using carry chains as variable delay elements. Regards, Gabor
Reply by ●January 26, 20102010-01-26
On Jan 26, 10:54=A0am, "Pallavi" <pallavi_mp@n_o_s_p_a_m.rediffmail.com> wrote:> > Hi, John, > > Can I use gates(adder,AND gate,etc.) to generate delays. If yes what shou=ld> be the input and output. I'm just supposed to do simulation, no physical > implementation required. If would be really helpful if I could get some > help on this. Thanks. =A0 =A0 =A0 > > --------------------------------------- =A0 =A0 =A0 =A0 > Posted throughhttp://www.FPGARelated.comThis is very advanced stuff not intended for mainstream use. It's quite possible that the simulation output will not have proper values for the routing delays and the delays of the individual elements. But maybe it'll work. Gabor is correct: you need to instantiate your LUT4 and/or MUXCY primitives so the synthesizer doesn't optimize them away. I wanted to develop an alternative to the Delay Locked Loop used in many Xilinx devices allowing me to have full control over the characteristics so I could determine where in the phase of my "ring oscillator" a signal edge occurred. I consider myself an expert, expecially at this level of detail. I couldn't come up with a solid approach in a reasonable amount of time. A ring oscillator with LUTs are best put together within one CLB which requires a significant amount of time figuring out intra-CLB routing delays to have decent delay matching. I couldn't do what I wanted within one CLB so I used two adjacent CLBs trying to get good, tight delays between those basic architecture elements. The attempt at using a carry chain is hampered by the time needed to take a signal off the carry chain and insert the inversion back to the bottom. The delays from these elements are affected by other things that happen within the FPGA - voltage rails, temperatures, nearby activity - such that the oscillators need constant calibration or measurement to match up to something external. If you just want a delay across a small range - 10s of nanoseconds, perhaps - you can get the resolution down to about the delay of a LUT but you'll have a full scale error that's significant. Using a chain of LUTs that are manually placed and perhaps manually routed as well, you can connect a series of LUT4 primitives configured as inverters; if you connect them as buffers you'll get different delays for rising edges than for falling edges. Getting the signal selectively injected into the chain or multiplexed out of the chain with deterministic delays is ugly. You will be faced with an absolute minimum delay, a delay full-scale that's difficult or impossible to calibrate, and poor consistency in the delay steps (the equivalent of poor differential linearity in Analog to Digitial or Digital to Analog converters). I don't want to provide you with a solution because I know a good solution is hard work. I want to set up your expectations. And you haven't told us what is required of you in the "physical implementation" you mentioned in the beginning.
Reply by ●January 26, 20102010-01-26
On Tue, 26 Jan 2010 09:55:22 -0800 (PST), John_H wrote:>Getting the signal selectively injected >into the chain or multiplexed out of the chain >with deterministic delays is ugly.Understood. This is not my area at all, so I'm just speculating (and hoping to learn)... Is it possible to make the chain go up a column of LUTs, through only one of the LUTs in each slice along the way, and then back down through the other halves of the slices? In that way you could get a hairpin-shaped chain, with the possibility of bridging it at any point along its length; the selectable bridges, each being within one slice, would be rather predictable; the injection/extraction points are of course fixed, at the "open" end of the hairpin. The delay resolution would be two LUT delays rather than one, which might be a drawback. thanks -- Jonathan Bromley
Reply by ●January 26, 20102010-01-26
On Jan 26, 12:34=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> On Tue, 26 Jan 2010 09:55:22 -0800 (PST), John_H wrote: > >Getting the signal selectively injected > >into the chain or multiplexed out of the chain > >with deterministic delays is ugly. > > Understood. > > This is not my area at all, so I'm just speculating > (and hoping to learn)... > > Is it possible to make the chain go up a column of > LUTs, through only one of the LUTs in each slice along > the way, and then back down through the other halves of > the slices? =A0In that way you could get a hairpin-shaped > chain, with the possibility of bridging it at any point > along its length; the selectable bridges, each being > within one slice, would be rather predictable; the > injection/extraction points are of course fixed, at > the "open" end of the hairpin. > > The delay resolution would be two LUT delays rather > than one, which might be a drawback. > > thanks > -- > Jonathan BromleyHello Jonathan, Not with the carry chains, as they all run in the same direction. Regards, John McCaskill www.FasterTechnology.com
Reply by ●January 26, 20102010-01-26
On Jan 26, 1:34=A0pm, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com> wrote:> On Tue, 26 Jan 2010 09:55:22 -0800 (PST), John_H wrote: > >Getting the signal selectively injected > >into the chain or multiplexed out of the chain > >with deterministic delays is ugly. > > Understood. > > This is not my area at all, so I'm just speculating > (and hoping to learn)... > > Is it possible to make the chain go up a column of > LUTs, through only one of the LUTs in each slice along > the way, and then back down through the other halves of > the slices? =A0In that way you could get a hairpin-shaped > chain, with the possibility of bridging it at any point > along its length; the selectable bridges, each being > within one slice, would be rather predictable; the > injection/extraction points are of course fixed, at > the "open" end of the hairpin. > > The delay resolution would be two LUT delays rather > than one, which might be a drawback. > > thanks > -- > Jonathan BromleyActually the delay resolution would be two carry chain delays which is much shorter than 2 LUT delays. That would certainly make life easier, but as John McC noted, you only get chain propagation in one direction. I once tried to generate a variable delay element by feeding the same signal into a number of taps in the same carry chain. It turned out that the signal routed up the chain in the same direction as the carry, and the routing delay matched the carry chain delay almost perfectly, so changing the tap made essentially no difference at all. This is really the sort of thing you need to know the guts of your chip to implement. regards, Gabor
