In system memory editor of Altera for Xilinx

On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote:

> Antti,
> 
> Oh, you are so kind!
> 
> Really, the way to set initial conditions is in your HDL code.
> 
> For BRAM, there is a whole app note on how to use the data2bram utility
> to set BRAM contents.
> 
> http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf
> 
> I would argue that we are (trying to) prevent poor coding practices,
> which lead to errors, and poor HDL code,
> 
> Austin

Austin,

The ability to change memories or registers has nothing to do with poor 
coding practices. When you are running a hardware testbench it would be 
incredibly useful to be able to change the contents of a register in real 
time rather then having to place and route the design again. Changing a 
register allows you to be able to select different tests or test 
conditions. There also ought to be a way to add some signals to ChipScope 
or SignalTap in a few minutes. The so called quick recompiles aren't 
quick at all. Speed of adding a few additional signals is an area where 
both tools are deficient.

I use both Xilinx and Altera tools. The place where Xilinx tools are 
noticeably inferior to Altera's is with ChipScope vs SignalTap. The 
ChipScope software doesn't even under stand the concept of buses, it 
requires you to group things together by hand which is a tedious process, 
SignalTap does this automatically. 

I wonder if either Xilinx or Altera's tools people bother to look at each 
others stuff. Chipscope hasn't been improved for years, there is no 
excuse for it to be as poor as it is, the Xilinx people ought to look at 
SignalTap and at least match it's features. Just to be even handed about 
this, the Altera people would benefit from looking at Xilinx's method of 
doing timing analysis. Altera introduced a new timing tool a couple of 
years ago and it still sucks. Xilinx produces an easy to read timing 
report that you can look at in Emacs. It shows the fanout and delays of 
each stage of the worst case paths, formatted as one line per level. 
Xilinx also figures out derivative clocks automatically, all you have to 
do is specify the reference clock speed and the tools automatically 
figures out the rates and phase relationships of all of the outputs of 
the PLL or DCM. The Altera tools forces you to do that by hand, what's 
worse is that you can't even do it using the clock names, you have to 
figure out the path to the output port of the PLL. Altera's report format 
is utterly unusable, you are forced to look at worst case paths in the 
GUI and what it puts out is nearly unreasonable. The bottom line is that 
I do all of my timing closure using Xilinx tools even if the design is 
targeted at an Altera part. Once the Xilinx version meets timing I run it 
through Quartus and hope that I only have a couple of paths that need 
fixing.


 

On Jan 29, 7:30=A0pm, General Schvantzkoph <schvantzk...@yahoo.com>
wrote:
> On Fri, 29 Jan 2010 08:13:56 -0800, austin wrote:
> > Antti,
>
> > Oh, you are so kind!
>
> > Really, the way to set initial conditions is in your HDL code.
>
> > For BRAM, there is a whole app note on how to use the data2bram utility
> > to set BRAM contents.
>
> >http://www.xilinx.com/itp/xilinx92/books/docs/d2m/d2m.pdf
>
> > I would argue that we are (trying to) prevent poor coding practices,
> > which lead to errors, and poor HDL code,
>
> > Austin
>
> Austin,
>
> The ability to change memories or registers has nothing to do with poor
> coding practices. When you are running a hardware testbench it would be
> incredibly useful to be able to change the contents of a register in real
> time rather then having to place and route the design again. Changing a
> register allows you to be able to select different tests or test
> conditions. There also ought to be a way to add some signals to ChipScope
> or SignalTap in a few minutes. The so called quick recompiles aren't
> quick at all. Speed of adding a few additional signals is an area where
> both tools are deficient.
>
> I use both Xilinx and Altera tools. The place where Xilinx tools are
> noticeably inferior to Altera's is with ChipScope vs SignalTap. The
> ChipScope software doesn't even under stand the concept of buses, it
> requires you to group things together by hand which is a tedious process,
> SignalTap does this automatically.
>
> I wonder if either Xilinx or Altera's tools people bother to look at each
> others stuff. Chipscope hasn't been improved for years, there is no
> excuse for it to be as poor as it is, the Xilinx people ought to look at
> SignalTap and at least match it's features. Just to be even handed about
> this, the Altera people would benefit from looking at Xilinx's method of
> doing timing analysis. Altera introduced a new timing tool a couple of
> years ago and it still sucks. Xilinx produces an easy to read timing
> report that you can look at in Emacs. It shows the fanout and delays of
> each stage of the worst case paths, formatted as one line per level.
> Xilinx also figures out derivative clocks automatically, all you have to
> do is specify the reference clock speed and the tools automatically
> figures out the rates and phase relationships of all of the outputs of
> the PLL or DCM. The Altera tools forces you to do that by hand, what's
> worse is that you can't even do it using the clock names, you have to
> figure out the path to the output port of the PLL. Altera's report format
> is utterly unusable, you are forced to look at worst case paths in the
> GUI and what it puts out is nearly unreasonable. The bottom line is that
> I do all of my timing closure using Xilinx tools even if the design is
> targeted at an Altera part. Once the Xilinx version meets timing I run it
> through Quartus and hope that I only have a couple of paths that need
> fixing.

thanks General!

yes, both REGISTER (LUT and distributed RAM) as BRAM can be changed
via JTAG and ability todo so would be of benefit for Xilinx Customers.
As of chipscope
hm, it isnt that bad, but it could be better.

As of of using X tools, eh I use X tools to make Actel designs..:)
I setup Xilinx project, create BRAM modules that look like actel RAM's
and then run that on some Xilinx board with Chipscope added to the
design.
and finally will then replace some modules to target Actel

Antti

General Schvantzkoph <schvantzkoph@yahoo.com> writes:

> The ability to change memories or registers has nothing to do with poor 
> coding practices. When you are running a hardware testbench it would be 
> incredibly useful to be able to change the contents of a register in real 
> time rather then having to place and route the design again.

I seem to remember changing BRAM contents with FPGA editor. Should be
faster than going through the whole place and route flow.

On Jan 30, 8:38=A0pm, Anssi Saari <a...@sci.fi> wrote:
> General Schvantzkoph <schvantzk...@yahoo.com> writes:
> > The ability to change memories or registers has nothing to do with poor
> > coding practices. When you are running a hardware testbench it would be
> > incredibly useful to be able to change the contents of a register in re=
al
> > time rather then having to place and route the design again.
>
> I seem to remember changing BRAM contents with FPGA editor. Should be
> faster than going through the whole place and route flow.

well yes you can also sometimes data2mem, but that isnt same things
as chaning it over JTAG as it possible with Altera Quartus

Antti

On 29 ene, 11:22, "jmunir" <jmu...@gts.tsc.uvigo.es> wrote:
> Hi!,
>
> I have been working with Altera FPGAs for a long time and now I have to
> deal with Xilinx ones. Until now, with Quartus II I have been able to
> manage the content of different registers and memories with 'In system
> memory editor' and I would like to do the same with Xilinx. I cannot find
> the right application to do it. Could you tell me which one I need or how=
 I
> can do it?
>
> Thanx
>
> J.
>
> --------------------------------------- =A0 =A0 =A0 =A0
> Posted throughhttp://www.FPGARelated.com

To debuging proposes you can try JTAG loader, part of KCPSM3 and can
be downloaded from Xilinx web site.
May be you need do some "bricolage" but work fine.

Walter

>
> To debuging proposes you can try JTAG loader, part of KCPSM3 and can
> be downloaded from Xilinx web site.
> May be you need do some "bricolage" but work fine.
>
> Walter

Hi Walter,

well it depends, for me, I can write own JTAG tools and JTAG IP cores
as i please, and do get things done as needed.

The OP question was more about FPGA vendor own support tools that use
vendor JTAG tools and adapters and can modify the FPGA registers and
BRAM in generic, without ANY support in user VHDL using the
configuration logic bypass functions, its like partial dynamic
reconfiguration,  maybe it understood now better. This is possible and
supported by Altera Quartus, and NOT supported by any Xilinx tools.

Antti

Antti escribi�:
>> To debuging proposes you can try JTAG loader, part of KCPSM3 and can
>> be downloaded from Xilinx web site.
>> May be you need do some "bricolage" but work fine.
>>
>> Walter
> 
> Hi Walter,
> 
> well it depends, for me, I can write own JTAG tools and JTAG IP cores
> as i please, and do get things done as needed.
> 
> The OP question was more about FPGA vendor own support tools that use
> vendor JTAG tools and adapters and can modify the FPGA registers and
> BRAM in generic, without ANY support in user VHDL using the
> configuration logic bypass functions, its like partial dynamic
> reconfiguration,  maybe it understood now better. This is possible and
> supported by Altera Quartus, and NOT supported by any Xilinx tools.
> 
> Antti
> 
>

Hi Antti,

In my projects, many times I need write software/firmware and hardware 
only to debugging.

I try to answer the original post; how solve a specific problem with a 
more or less simple general solution; JTAGLoader or a simple 
VHDL/Verilog UART plus a 8 U$D USB-RS232-TLL adapter can be used to 
modify a design for debugging without need write software, if the 
designer designs for verification.

Others is Xilinx's tools, well, I use Xilinx's tools since many years, 
the tool is today (I use ISE 10) several times more friendly but not 
necessarily more productive than older Xilinx's tools.

The Xilinx's tools are a complex piece of software and as T.Hoare 
sentence at '80.

"There are two ways of constructing a software design: One way is to 
make it so simple that there are obviously no deficiencies, and the 
other way is to make it so complicated that there are no obvious 
deficiencies. The first method is far more difficult."

Thinking in my daily work, memory editor could be a nice feature but not 
necessarily in the firsts places of my list of necessary features.

It may be a good exercise for us all, list the ISE features that we use 
daily, occasionally or never used and which features would be 
interesting to add.

If we reach a consensus, Xilinx perhaps listen to us.

Walter.

--- news://freenews.netfront.net/ - complaints: news@netfront.net ---

On Jan 29, 12:11=A0pm, Antti <antti.luk...@googlemail.com> wrote:
> On Jan 29, 7:01=A0pm, austin <aus...@xilinx.com> wrote:
>
>
>
> > Antti,
>
> > "If Xilinx cared about the customers...."
>
> > Cruel, and inappropriate.
>
> > Of course we care (deeply) about our customers!
>
> > "Because Xilinx does not have Tool-A, they have no concern for
> > customers..."
>
> > It would be equally true then to say because the 'other guy' has no
> > domain specific platforms, that they have zero regard for their
> > customers, and force them to re-invent the wheel before they even
> > begin a project ... (which in my humble opinion is all true)
>
> > So, let us refrain from 'name calling', =A0one could waste a great deal
> > of time,
>
> > Austin
>
> ah, relax..
>
> both X and A care for the shareholders.
>
> but the topic about the "memory editor" is well, it would be SO EASY
> for Xilinx todo,
> but it has not been done. some 3rd party could do, i could do it, but
> it would be much
> more work for me todo it properly as it would be for xilinx, besides
> because Xilinx
> does not open up the xilinx usb cable protocol i could not support
> xilinx cables
> from my tool, so it would be pointless todo.

I like the way that Austin gets all hot under the collar when you say
"extreme" things about Xilinx, which we all know to take with a grain
of salt, (even if we pretty much agree with them) but he completely
ignores the real issue being discussed.  His reply, "we are (trying
to) prevent poor coding practices,
which lead to errors" seems to be saying that the programmer is not to
be trusted with tools that allow him to work the way he wants.  Geeze,
there are any number of reasons why a designer would want to
manipulate the initial values in the BRAMs "on the fly".  Obviously
that is why Altera provides these tools.  Otherwise we are left to
think that Altera wants to promote "poor coding practices" and
errors.


> there are two reasons why Xilinx does not have memory editor
> 1) there are some silicon problems, errata, bugs with the silicon
> preventing the usefulnes of the tool
> 2) Xilinx just doesnt care to offer this tool
>
> I see no other reasons. you can choose. either silicon problems, or
> lazy programmers.
> or management issues. i figured out 3rd option.
>
> but.. DATA2MEM is MUCH more important (yeah for the customers) then
> the memory editor
> and well Altera has no data2mem possibility at all, what is real
> problem.
>
> Xilinx has what is really needed, and misses on optional "good to
> have" thing that is not
> that vital.
>
> Antti

Personally, I think both tools are very useful.  Once a design is
compiled and a bit file produced that works properly, it can be very
useful to produce different versions of the bit stream with different
data in the BRAMs.  But during debug it can be much more expedient to
download the BRAM data on the fly as needed.  Potentially it could
even be useful to download the BRAM contents ov er JTAG in the field,
but I see that as a very limited application.  But I can assure you
that if either company had just one very large customer who requested
a tool like this, they would get it.  So most likely, each company has
produced the tool that their customers have requested.

Rick

On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es>
wrote:
> So, my question is:
>
> When I implement a block and I would like to control several of his
> parameters to test its behaviour, do I have to recompile each time I want
> to change one of them? :O
>
> That has not sense! It is impractical!
>
> J.

I don't think you need to recompile the HDL.  You need to produce a
new bit stream from the original bitstream.  Still, this requires a
number of steps, which can be done in one step with a JTAG tool.

Rick

On Feb 1, 7:36=A0am, rickman <gnu...@gmail.com> wrote:
> On Jan 29, 12:06=A0pm, "jmunir" <jmunir@n_o_s_p_a_m.gts.tsc.uvigo.es>
> wrote:
>
> > So, my question is:
>
> > When I implement a block and I would like to control several of his
> > parameters to test its behaviour, do I have to recompile each time I wa=
nt
> > to change one of them? :O
>
> > That has not sense! It is impractical!
>
> > J.
>
> I don't think you need to recompile the HDL. =A0You need to produce a
> new bit stream from the original bitstream. =A0Still, this requires a
> number of steps, which can be done in one step with a JTAG tool.
>
> Rick

Hi,

If you have a design where you want to modify the BRAM contents,
data2mem is the tool to use.
It can modify an existing bitfile and creates a new bitfile with the
new BRAM contents.
After you have created the .bmm file, it's just one call to data2mem
to create a new bitfile with modified BRAM contents.
It takes a few seconds to finish.

If you just want to toggle some registers down in the target, you can
use Chipscope VIO which allows you to modify signal values in target
using JTAG.

I agree that it would be good to have a tool that allow you full
control of everything in the device over JTAG but I can also think of
10+ other tools that would be good to have.
Xilinx doesn't have an infinite number of resources for doing tools
and we have to pick which one we should do.

One can argue that a comprehensive JTAG debug tool should be one of
them but as today, Xilinx has data2mem and chipscope.
It allows customers accomplish what they want although it might not be
in easiest way for everyone.


G=F6ran