Connecting ADC chip to sparta 3 a dsp

hi there

  I have an ADC chip which is working in the LVDS mode. 
 The data out(D0+,D0-,......D13+ and D13-),along with data clock
out(DC0+,DC0-)
and out of range(OUR) are connected physically to Sparta 3a dsp.

 My question is how do I directly collect these LVDS signals in my sparta
3a dsp core.

 How do I get back my data in aa format I can work on?





	   
					
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On Feb 1, 7:32=A0am, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote:
> hi there
>
> =A0 I have an ADC chip which is working in the LVDS mode.
> =A0The data out(D0+,D0-,......D13+ and D13-),along with data clock
> out(DC0+,DC0-)
> and out of range(OUR) are connected physically to Sparta 3a dsp.
>
> =A0My question is how do I directly collect these LVDS signals in my spar=
ta
> 3a dsp core.
>
> =A0How do I get back my data in aa format I can work on?


It is a little scary reading this question.  It makes me think you
don't understand that an LVDS receiver only has two signals on the
pins, but is converted to a single signal by the receiver.  Is that
what you are missing?  If so, you need to make sure your LVDS signals
are going to the receivers in matched pairs.  If you already
understand this, then I am not clear on what you don't understand.

In general, to use inputs to an FPGA, you have signal names in your
HDL code which are inputs and outputs to the top level module.  A
separate file, typically created using a special editor in the GUI,
specifies the details of how these signals are to be mapped to the I/O
pins.  Each maker has their own format for this file and typically
other details are specified here, such as the I/O type (TTL, CMOS,
LVDS, etc...), voltage levels, drive strength, etc...   Often this
same file also contains the timing constraints to be applied to the
design while it is routed by the tool and analyzed to see if it meets
timing.

Is that what you needed?

Rick

On Feb 1, 7:27=A0am, rickman <gnu...@gmail.com> wrote:
> On Feb 1, 7:32=A0am, "lakshmi3489" <lakshmi.dorav...@gmail.com> wrote:
>
> > hi there
>
> > =A0 I have an ADC chip which is working in the LVDS mode.
> > =A0The data out(D0+,D0-,......D13+ and D13-),along with data clock
> > out(DC0+,DC0-)
> > and out of range(OUR) are connected physically to Sparta 3a dsp.
>
> > =A0My question is how do I directly collect these LVDS signals in my sp=
arta
> > 3a dsp core.
>
> > =A0How do I get back my data in aa format I can work on?
>
> It is a little scary reading this question. =A0It makes me think you
> don't understand that an LVDS receiver only has two signals on the
> pins, but is converted to a single signal by the receiver. =A0Is that
> what you are missing? =A0If so, you need to make sure your LVDS signals
> are going to the receivers in matched pairs. =A0If you already
> understand this, then I am not clear on what you don't understand.
>
> In general, to use inputs to an FPGA, you have signal names in your
> HDL code which are inputs and outputs to the top level module. =A0A
> separate file, typically created using a special editor in the GUI,
> specifies the details of how these signals are to be mapped to the I/O
> pins. =A0Each maker has their own format for this file and typically
> other details are specified here, such as the I/O type (TTL, CMOS,
> LVDS, etc...), voltage levels, drive strength, etc... =A0 Often this
> same file also contains the timing constraints to be applied to the
> design while it is routed by the tool and analyzed to see if it meets
> timing.
>
> Is that what you needed?
>
> Rick

It actually isn't that trivial to hook up an LVDS part to a Spartan3A,
because there don't seem to be any simple, broadly-applicable examples
floating around.  What is out there is a lot of contradictory,
confusing advice, and the docs aren't very helpful at all.

In particular, it's unclear what declarations and attributes go into
the .ucf file and what can be declared on the HDL side.  After some
Googling and trial-and-error work, I ended up with a .UCF section like
this:

net "BUS_0_P<15>"    LOC =3D "B15" | IOSTANDARD =3D "LVDS_33" | DIFF_TERM
=3D TRUE;

net "BUS_0_N<15>"    LOC =3D "B14" | IOSTANDARD =3D "LVDS_33" | DIFF_TERM
=3D TRUE;

(repeat for other bus lines 14...0)

... and the following Verilog interface:

module LTC2217
(
   input ADC_0_P_CLK,
   input ADC_0_N_CLK,

   input signed [15:0] BUS_0_P,
   input signed [15:0] BUS_0_N,
   (...)
);

   //
   // LVDS buffers
   //

   wire [15:0] B0;
   wire ADC_0_CLK;

   IBUFGDS #(.DIFF_TERM("TRUE"),
            .IOSTANDARD("LVDS_33")
   ) SOURCE_SYNC_CLOCK_IN
      (
      .I(ADC_0_P_CLK),
      .IB(ADC_0_N_CLK),
      .O(ADC_0_CLK));

   genvar i;
   generate
   for (i=3D0; i <=3D 15; i =3D i + 1)
   begin: loop0

      IBUFDS #(.DIFF_TERM("TRUE"),
               .IOSTANDARD("LVDS_33")
      ) ibuf_d0
         (
         .I(BUS_0_P[i]),
         .IB(BUS_0_N[i]),
         .O(B0[i]));

   end
   endgenerate

In this case B0 is the name of the ADC bus that would be declared as a
single-ended input if LVDS weren't being used, and ADC_0_CLK is its
data-ready signal.

I'm not necessarily claiming that this is the "right" way to do it,
but it worked in my case.

-- john, KE5FX