How good are Actel tools

I know Antti has a lot of experience with Actel, so I expect to hear
from him, but I am sure there are others out there with experience of
Actel tools.  A customer of mine has told me that he used Actel for a
project some 4 or 5 years ago and had a problem with the tools that
Actel could not give a fix for.  I don't recall how he worked around
it and I am sure that particular issue has been fixed, but I now have
the impression that the Actel tools are not as good as tools from the
other three.  I seem to recall some significant issues being discussed
here.

Can anyone confirm or dispute it the relative quality of Actel tools?
Am I mistaken about them?

Rick

rickman wrote:
> Can anyone confirm or dispute it the relative quality of Actel tools?
> Am I mistaken about them?

I am speaking only about my own personal point of view of mine...
and under Windows (have not yet had time to re-try under Fedora)

The Actel tools take a while to get used too,
like most big SW suites. It's its own world...
It is not particularly terrible, I can do
mostly what I want, inside the bounds of reality
and the target chip's capacity.

I have not tried to "hack" things because I don't
want to be dependent on a specific too, I do my stuff
in VHDL and add a constraint file (which can be a bitch
is a few situations but not a real limit).
The latest version of Libero seems OK,
it's not groundbreaking but I sense some care
for user friendliness (which is a whole different
concept in itself if the FPGA world ;-D)

When badly blocked, I could contact my local FAE
and even a local Actel office. The usefulness of
the  online reporting/case tool is ... mitigated
but can be tried if a project is badly screwed.

Oh, and comp.arch.fpga is very helpful too ;-)

So I can say that "Actel works for my case" and
I'm fine with it. It just takes a lot of time
to get used to the rules and design of this particular "world",
so it's usual to ask impossible or difficult things
when learning. Later, one does design things around
the chip's capabilities instead of the contrary,
and it goes smoothly (after a few iterations ;-D)

I'm curious to read other people's impressions...

> Rick
yg

-- 
http://ygdes.com / http://yasep.org

On 4 Feb., 12:01, whygee <y...@yg.yg> wrote:
> > Can anyone confirm or dispute it the relative quality of Actel tools?
> > Am I mistaken about them?
>
> The Actel tools take a while to get used too,
> like most big SW suites. It's its own world...
> It is not particularly terrible, I can do
> mostly what I want, inside the bounds of reality
> and the target chip's capacity.

For "normal" projects I have the same opinion.

I'm using Actel since nearly 10 years now in a lot of projects for
several technologies.

Actel provides a crippled version of Modelsim like most other tools
(Xilinx,...) I can't say anything about this, as I have access to full
Modelsim.
The synthesis tool provided for free is Synplicity. I would consider
this tool as usable in standard projects and would be surprised if xst
performs better in overall. But Synplify itself as well as in
combination with the libraries of Actel for several technologies may
cause trouble if you need to squeeze the technologie or leave the
"main stream" of hdl coding. Synplicity provides no direct support and
Actel can't provide the needed support in some cases. I remember
several problems which could not be fixed in a reasonable amount of
time by Actel.

The major used tool from Actel is desiger (the P&R+Layout tool). This
tool is quite good if you're used to it and it took me less time to
get the first design done than my experiences with xilinx.
But the manual layout itself is in each technology different (which I
would consider major drawback). I personaly dislike the manual layout
or pinassignment per GUI of ProAsic devices, while the story is
complete different for SX-S.

You may encounter problems when doing large designs on new released
technologies. The windows version is atm only usable in 32-bit OS
which will bite you when doing very large designs.

bye Thomas

On Feb 5, 4:53=A0am, Thomas Stanka <usenet_nospam_va...@stanka-web.de>
wrote:
> On 4 Feb., 12:01, whygee <y...@yg.yg> wrote:
>
> > > Can anyone confirm or dispute it the relative quality of Actel tools?
> > > Am I mistaken about them?
>
> > The Actel tools take a while to get used too,
> > like most big SW suites. It's its own world...
> > It is not particularly terrible, I can do
> > mostly what I want, inside the bounds of reality
> > and the target chip's capacity.
>
> For "normal" projects I have the same opinion.
>
> I'm using Actel since nearly 10 years now in a lot of projects for
> several technologies.
>
> Actel provides a crippled version of Modelsim like most other tools
> (Xilinx,...) I can't say anything about this, as I have access to full
> Modelsim.
> The synthesis tool provided for free is Synplicity. I would consider
> this tool as usable in standard projects and would be surprised if xst
> performs better in overall. But Synplify itself as well as in
> combination with the libraries of Actel for several technologies may
> cause trouble if you need to squeeze the technologie or leave the
> "main stream" of hdl coding. Synplicity provides no direct support and
> Actel can't provide the needed support in some cases. I remember
> several problems which could not be fixed in a reasonable amount of
> time by Actel.
>
> The major used tool from Actel is desiger (the P&R+Layout tool). This
> tool is quite good if you're used to it and it took me less time to
> get the first design done than my experiences with xilinx.
> But the manual layout itself is in each technology different (which I
> would consider major drawback). I personaly dislike the manual layout
> or pinassignment per GUI of ProAsic devices, while the story is
> complete different for SX-S.
>
> You may encounter problems when doing large designs on new released
> technologies. The windows version is atm only usable in 32-bit OS
> which will bite you when doing very large designs.
>
> bye Thomas

"atm only"?  Is that a typo?  It seems to read ok if the "atm" is left
out entirely.

Rick

On Fri, 5 Feb 2010 06:44:18 -0800 (PST), rickman wrote:

>"atm only"?  Is that a typo?  It seems to read ok if the "atm" is left
>out entirely.

atm ~= "at the moment" ?
-- 
Jonathan Bromley

On Feb 5, 9:54=A0am, Jonathan Bromley <jonathan.brom...@MYCOMPANY.com>
wrote:
> On Fri, 5 Feb 2010 06:44:18 -0800 (PST), rickman wrote:
> >"atm only"? =A0Is that a typo? =A0It seems to read ok if the "atm" is le=
ft
> >out entirely.
>
> atm ~=3D "at the moment" ?
> --
> Jonathan Bromley

PUTMNOAAA*

Rick



*People Use Too Many Non Obvious Abbreviations And Acronyms

>
>Can anyone confirm or dispute it the relative quality of Actel tools?
>Am I mistaken about them?
>
>Rick
>

I've not used a wide range of FPGA tool suites, just the other major two,
but I have found that Actel's, have been the worst yet. 

I don't do very large of complex designs, just stuff for single FPGAs, and
don't really play with the complex features of the suite, so I can't
comment on those areas (where they might actually impress).

The silver lining is that they are in bed with Synplify/Synopsys so you get
that for synthesis, but the pain starts with their layout backend tool.

I run everything Ubuntu GNU/Linux, and prefer batch-mode to a GUI
interface. This in itself is a fair challenge, you must export
LD_LIBRARY_PATHs whenever you run any of their tools (not so bad, I
guess.... but why the need?!) They're painful to use, too, in whenever you
launch a tool, there's about 5 minutes of it sitting there doing nothing,
as far as I can tell. This is really productive when all you need to do is
check if changes to a PDC are OK.

A place-and-route run always leaves my machine reeling for memory
afterwards, it somehow manages to chew through a couple of gig of RAM and
even make things start swapping. I'm convinced there's several memory
holes, but don't have the will to run this behemoth in valgrind.

Their tools take far longer than any other vendors for the same size design
on a similar-sized FPGA, and then you have the issue of any net with fanout
> ~10  resulting in large net delays, so their performance is always
underwhelming.

So on the whole I find using the Libero/Designer suite is never the
highlight of my day.

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

>rickman wrote:
>> Can anyone confirm or dispute it the relative quality of Actel tools?
>> Am I mistaken about them?
>
>I am speaking only about my own personal point of view of mine...
>and under Windows (have not yet had time to re-try under Fedora)
>
>The Actel tools take a while to get used too,
>like most big SW suites. It's its own world...
>It is not particularly terrible, I can do
>mostly what I want, inside the bounds of reality
>and the target chip's capacity.
>
>

I have had similar experience.  I try to keep my flow tool independent in
this process Actel tools are ok.  I can take my design, add the files,
synthesize, PAR, and create a config file.  I have not had a reason to use
any of the additional tools and have not run into any major issues.

The learning curve for me was roughly the same as ISE or Quartus.  Possibly
a little less because of prior experience with other tools.

chris	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com