Board layout for FPGA

On 2/4/2010 1:41 PM, Nial Stewart wrote:
>>   Try to make room for bypass caps on the back of the board from the FPGA.
>
>
> You can use 0402 resistors with 0.6mm round pads on 1mm centres.
>
> This allows thm to be placed on the back of the BGA 'matching' the
> BGA pads, and allows almost one cap per power&  gnd pair.
>
> Check with your assembly house that they're happy with this, mine does it
> no problem (they built a couple of boards with 0.5mm pads before telling
> me to make them bigger).
>
>
>
> Nial
>
I'll second that. It works for me. Make the pad size the limit of the 
PCB fab's spec.

Cheers, Syms.

Awesome, thanks for the good information!

John,
I don't think I can get away with only the outer two rows of balls,
I'll probably need the two inside of that as well-- I was thinking of
breaking out the outer two on one signal layer and the inner two in
another, as suggested in the Xilinx app note I saw. It was a tight
squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
is the standard offering of the board house we're using.. it's
possible to ask for smaller, for an extra chunk of change.

Are there any examples out there of how to route memory chips on a
bus? I'm kind of new to routing and don't really know what the
strategy is for this kind of thing. I was thinking about this when
designing a board to interface to expansion headers on a dev board for
a first prototype, but I couldn't think of a way to do it with just
two layers, so I gave each chip its own lines in that case since I had
plenty of I/O.
I can imagine a scheme in which there are vias on each line going into
the first chip, connecting to wires on another layer to carry the
lines to the other chip where they are brought back to the component
side with more vias, but that's all I can come up with off the top of
my head

RCIngham, thanks for the heads-up on the EEPROM. I guess that the idea
is to have non-volatile data in it, and copy it to a section of SRAM
on power-up and then just read from SRAM during normal operation, but
I will still probably have to think about the time to 'Z' when
designing that data transfer part of the software.

cheers,

Steve

>
> Are there any examples out there of how to route memory chips on a
> bus? I'm kind of new to routing and don't really know what the
> strategy is for this kind of thing. I was thinking about this when
> designing a board to interface to expansion headers on a dev board for
> a first prototype, but I couldn't think of a way to do it with just
> two layers, so I gave each chip its own lines in that case since I had
> plenty of I/O.


Now that I think of it, I suppose I could make the bus connection job
a little simpler if I take advantage of the fact that RAM is "random
access," so the address/data line numbers from chip to chip don't
necessarily have to match up. Then the address/data lines could be
connected in whatever order is easiest and cleanest, since on the FPGA
side the data would go in and come out in the desired order either
way.
Would this for any reason be a bad design practice?

Steve

On Feb 4, 4:04=A0am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:
> Thanks for the input so far, guys!
>
> I will have two SRAM chips and one parallel EEPROM in one memory
> space, and one additional RAM chip in a separate memory space so I
> know for sure that that one gets its own dedicated address/control/
> data lines.
> I was just wondering if the signal integrity would be hurt by extra
> loading in chaining up the ones that are on the same bus, but I had a
> hunch that at these speeds it wouldn't be such a big problem.

Signal integrity is not normally a direct result of the "loading" of
the parts.  On most boards the effect of a pin on a bus is minimal.
If you split a run, like a fork in a river, it results in an impedance
mismatch and causes a reflection.  The end of a trace is a high
impedance which also is an impedance mismatch and causes a
reflection.  Three chips can be added to the board with trances as
short as maybe 2 inches.  This is 4 inches round trip or about half a
ns.  To avoid effects of reflection, the edge transition time should
be at least 3 ns.  That is a *slow* edge.  So expect noticeable
ringing.  As has been said, on the data and address lines, you just
need to extend the setup times to wait it out to sample the bus when
it has quieted down.  Figure three round trips or 1.5 ns extra.  But
the write enable signal should be clean.  The best way I know to do
that is to provide a separate write enable driver for each chip.  Then
you can use series impedance matching in a point to point wiring so
that the receiver does not see any effects from reflection.  Of course
this is assuming the write enable is the controlling pin when doing
writes.  Some designs use the chip select to control the write
timing.


> And probably I will be using 10ns RAMs (I haven't looked at the rise/
> fall times though) and keeping them physically as close as I can get
> them to the FPGA.. maybe about a centimeter away, tops.
> Looking at this old Digilent Spartan 3 board I have kicking around, I
> don't see any termination between the FPGA and the ISSI SRAMs on
> there, but each chip has its own address and data lines.. I dunno if
> that's good enough to use as an example or not though.

Are you going to try to use them as fast as possible?  That can be
hard.  If you can give each chip separate drivers for all signals, may
be able to keep the traces short enough to not see any reflection
effects.  I may have muffed the math on this.  That's the trouble with
rules of thumb.  If you recall them incorrectly, it can be hard to
spot the error.  Looking at this document,

http://techcircuits.net/docs/CriticalLength.pdf

It looks like I was overly pessimistic on the length.  The rule of
thumb seems to be 1/3 instead of 1/6 so a 1 ns rise time won't cause
significant reflections, but I'm not sure about that.  On page 7 they
use an analysis that I don't agree with.  Basically, they are saying
this is the critical edge of timing and I don't think it is that clear
cut.  I say use 1/6, but you can choose your own poison.


> As for the supply voltages, I'll be using a Virtex II, but this is the
> first time I have started to think about implementing my own board and
> thus needing to worry about power supplies, and I seemed to remember
> some of my dev boards in the past having a couple or three different
> regulators on board, but I didn't really think much about it. Looking
> at the datasheet though, you're right, Rick, it appears that I just
> need a single 1.5V supply for core voltage, and 3.3V for VCC_aux and
> all of my I/O. I should have checked that and had the numbers right
> before asking, sorry about that.

I would pick a newer family myself, but there is nothing wrong with a
Virtex II device.  However, a newer family will be faster, lower power
and you will likely get better support.  Of course you can overdo that
too.  If you try to use the newest family, you may not get parts for
months and the tools may be a bit buggy...  But Virtex 2???  Why not
Virtex 5 or even Virtex 4?  The Spartan 3 chips are pretty good and
have been updated quite a bit although  I don't recall which are the
latest and greatest.  I know the S3 parts are FAPP not recommended for
new designs (at least by those of us here I expect) and the S3A parts
are pretty old at this point.  Anyone, what are the newer S3x parts?

If you want to keep the power supply simple, Lattice has XP and
perhaps XP2 parts that use a single 3.3 volt supply and internally
drop it to the core voltage.


> So if I need power planes for both of these voltages, do they each
> need their own layer or can I arrange it carefully in one layer?

Yes, you can use one layer.  I have a very tiny board <1" x 4.5" with
no less than four power planes on one layer, +12, +5, +3.3 and an
audio 3.3.  There is another 1.8 volt plane in case I want to use an
FPGA with separate core voltage inputs, but that plane is on a
different layer shared with signal traces.  I can't stress enough the
importance of power planes in keeping switching noise down.  It is not
just a matter of adding a high frequency capacitor to the power rail,
it acts as a very low impedance transmission line connecting the
capacitors to the power pins of the chip.  It is counter intuitive,
but it actually is not so important to keep the caps so close to the
chip if you are using good power planes.  BTW, to maximize the
effectiveness of the power planes (read that as minimum impedance) you
want to have the power and ground plane as close together as
possible.  5 mils spacing should be practical and will go a long way
to doing a good job.

I found doing layout to be fun, but very intense!  Most design
requires you to go back and forth between specs and data sheets and
the schematic capture package.  Layout has some up front work getting
all the inputs and making the footprints, but then it just becomes a
really complex rubics cube with many possible solutions.  Your job is
to find one that is pretty good without spending tons of time on it.

When I did my first layout, I contacted a couple of colleges and asked
them to do a design review with me.  I was willing to pay them
consulting rates, but I was turned down.  It turned out ok in the end,
but there were a couple of things that likely would have been caught
in a review.  I am not very busy right now.  If you would like and
when you are ready, I'd be willing to go through a design review with
you without charge.  I'm pretty bored and would enjoy it.

Rick

On Feb 4, 5:28 am, Symon <symon_bre...@hotmail.com> wrote:
> On 2/4/2010 8:23 AM, David Brown wrote:
>
>
>
>
>
> > You have a lot more experience at this sort of thing than me, Rick, so
> > I'm a little wary of disagreeing with you. But I'm sure you'll tell me
> > if I get something wrong!
>
> > I don't see that you have to worry about any termination here. With fast
> > enough signal edges, you can get ringing - but that typically will not
> > matter because you don't sample the signals until the ringing has
> > subsided.
>
> > Ringing can cause a few problems - the overshoot/undershoot can go
> > outside the voltage range of the pins on the line, it can cause
> > interference for neighbouring signals, you can't read the signal while
> > it is ringing, and it can cause big trouble when connected to
> > edge-sensitive inputs. But most of these are not going to be a problem
> > in your case, I think.
>
> Dear David, Steve,
>
> Going "outside the voltage range of the pins on the line" can break the
> device. IIRC there are Xilinx appnotes which go into this problem in
> some detail; powering 3.3V with 3V was something I think they suggested!
> (See XAPP653)
> Also, the thing will probably fail any sort on electromagnetic
> compliance test that you would need to do before you sell this. And you
> are unlikely to be able to listen to 'The Archers' while this thing is
> in the room.
>
> To the OP, in the absence of micro-vias, I would recommend a 6 layer
> board. Maybe like this:-
>
> signal
> signal
> ground
> ground
> power/signal
> signal
>
> Keep all the layers as close together as your PCB manufacturer allows
> and make up the board thickness with the core between the two ground
> layers. Xilinx on the top. Route the powers, or use copper pours. Try to
> make room for bypass caps on the back of the board from the FPGA. This
> stack up will make it very difficult for a beginner to go wrong from an
> SI point of view, as ground is always near. This is particularly true if
> you have a nice spread of ground vias tying the two ground planes
> together. That doesn't mean you shouldn't simulate it with Hyperlynx,
> but I bet that won't happen! Always examine your ground plane pair at
> the end of the routing process to make sure you haven't cut any big
> slots in it with string of vias.
>
> Finally, _real_ engineers use DRAMs! ;-)
>
> HTH., Syms.
>
> p.s. Did I make it clear that the ground is important?

Everyone has their own way of doing things, but I would ask, why the
two ground planes?  I would have a ground plane and a power plane in
the center with a minimum thickness between them.  The spacing between
the ground/power plane and the signal plane is not so important.  What
is important is the characteristic impedance.  The lower the
impedance, the less it will radiate.  Of course, with thin traces you
have to have the signal plane to power/ground plane very small to get
a low impedance.  But if you have wide traces, you can open up the
plane spacing.  Since the outer layers are on the outside of the
board, they won't be very close to inside power/ground planes.  BTW,
you are aware that the power plane is just as effective as the ground
plane for determining the impedance.

Rick

On Feb 4, 9:43=A0pm, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:
> > Are there any examples out there of how to route memory chips on a
> > bus? I'm kind of new to routing and don't really know what the
> > strategy is for this kind of thing. I was thinking about this when
> > designing a board to interface to expansion headers on a dev board for
> > a first prototype, but I couldn't think of a way to do it with just
> > two layers, so I gave each chip its own lines in that case since I had
> > plenty of I/O.
>
> Now that I think of it, I suppose I could make the bus connection job
> a little simpler if I take advantage of the fact that RAM is "random
> access," so the address/data line numbers from chip to chip don't
> necessarily have to match up. Then the address/data lines could be
> connected in whatever order is easiest and cleanest, since on the FPGA
> side the data would go in and come out in the desired order either
> way.
> Would this for any reason be a bad design practice?
>
> Steve

In response to your other post about the bus timing, async memories
are the hardest to design I have found.  Sync memories like SDRAM are
a snap really, you just meet the setup and hold times and you are
done!  The rest is all just a state machine.  Async busses require all
sorts of timing numbers to be checked, I bet you will have over 30
numbers you will need to validate while doing this.  If you don't push
the timing to the max it can be much easier.

As to the randomization of the address/data lines, I have never done
that, but others have.   On the RAMs it shouldn't be a problem.  It
can even be worked around on the EEPROM if you have a program to remap
all the bits in the memory map, but that is such a PITA.  Getting your
schematic to optimize the layout without randomization of the lines
shouldn't be a real problem.

Rick

On Feb 5, 2:26=A0pm, rickman <gnu...@gmail.com> wrote:
> On Feb 4, 4:04=A0am, TSMGrizzly <sbatt...@yahoo.co.jp> wrote:
>
> > Thanks for the input so far, guys!
>
> > I will have two SRAM chips and one parallel EEPROM in one memory
> > space, and one additional RAM chip in a separate memory space so I
> > know for sure that that one gets its own dedicated address/control/
> > data lines.
> > I was just wondering if the signal integrity would be hurt by extra
> > loading in chaining up the ones that are on the same bus, but I had a
> > hunch that at these speeds it wouldn't be such a big problem.
>
> Signal integrity is not normally a direct result of the "loading" of
> the parts. =A0On most boards the effect of a pin on a bus is minimal.
> If you split a run, like a fork in a river, it results in an impedance
> mismatch and causes a reflection. =A0The end of a trace is a high
> impedance which also is an impedance mismatch and causes a
> reflection. =A0Three chips can be added to the board with trances as
> short as maybe 2 inches. =A0This is 4 inches round trip or about half a
> ns. =A0To avoid effects of reflection, the edge transition time should
> be at least 3 ns. =A0That is a *slow* edge. =A0So expect noticeable
> ringing. =A0As has been said, on the data and address lines, you just
> need to extend the setup times to wait it out to sample the bus when
> it has quieted down. =A0Figure three round trips or 1.5 ns extra. =A0But
> the write enable signal should be clean. =A0The best way I know to do
> that is to provide a separate write enable driver for each chip. =A0Then
> you can use series impedance matching in a point to point wiring so
> that the receiver does not see any effects from reflection. =A0Of course
> this is assuming the write enable is the controlling pin when doing
> writes. =A0Some designs use the chip select to control the write
> timing.
>
> > And probably I will be using 10ns RAMs (I haven't looked at the rise/
> > fall times though) and keeping them physically as close as I can get
> > them to the FPGA.. maybe about a centimeter away, tops.
> > Looking at this old Digilent Spartan 3 board I have kicking around, I
> > don't see any termination between the FPGA and the ISSI SRAMs on
> > there, but each chip has its own address and data lines.. I dunno if
> > that's good enough to use as an example or not though.
>
> Are you going to try to use them as fast as possible? =A0That can be
> hard. =A0If you can give each chip separate drivers for all signals, may
> be able to keep the traces short enough to not see any reflection
> effects. =A0I may have muffed the math on this. =A0That's the trouble wit=
h
> rules of thumb. =A0If you recall them incorrectly, it can be hard to
> spot the error. =A0Looking at this document,
>
> http://techcircuits.net/docs/CriticalLength.pdf
>
> It looks like I was overly pessimistic on the length. =A0The rule of
> thumb seems to be 1/3 instead of 1/6 so a 1 ns rise time won't cause
> significant reflections, but I'm not sure about that. =A0On page 7 they
> use an analysis that I don't agree with. =A0Basically, they are saying
> this is the critical edge of timing and I don't think it is that clear
> cut. =A0I say use 1/6, but you can choose your own poison.
>
> > As for the supply voltages, I'll be using a Virtex II, but this is the
> > first time I have started to think about implementing my own board and
> > thus needing to worry about power supplies, and I seemed to remember
> > some of my dev boards in the past having a couple or three different
> > regulators on board, but I didn't really think much about it. Looking
> > at the datasheet though, you're right, Rick, it appears that I just
> > need a single 1.5V supply for core voltage, and 3.3V for VCC_aux and
> > all of my I/O. I should have checked that and had the numbers right
> > before asking, sorry about that.
>
> I would pick a newer family myself, but there is nothing wrong with a
> Virtex II device. =A0However, a newer family will be faster, lower power
> and you will likely get better support. =A0Of course you can overdo that
> too. =A0If you try to use the newest family, you may not get parts for
> months and the tools may be a bit buggy... =A0But Virtex 2??? =A0Why not
> Virtex 5 or even Virtex 4? =A0The Spartan 3 chips are pretty good and
> have been updated quite a bit although =A0I don't recall which are the
> latest and greatest. =A0I know the S3 parts are FAPP not recommended for
> new designs (at least by those of us here I expect) and the S3A parts
> are pretty old at this point. =A0Anyone, what are the newer S3x parts?
>
> If you want to keep the power supply simple, Lattice has XP and
> perhaps XP2 parts that use a single 3.3 volt supply and internally
> drop it to the core voltage.
>
> > So if I need power planes for both of these voltages, do they each
> > need their own layer or can I arrange it carefully in one layer?
>
> Yes, you can use one layer. =A0I have a very tiny board <1" x 4.5" with
> no less than four power planes on one layer, +12, +5, +3.3 and an
> audio 3.3. =A0There is another 1.8 volt plane in case I want to use an
> FPGA with separate core voltage inputs, but that plane is on a
> different layer shared with signal traces. =A0I can't stress enough the
> importance of power planes in keeping switching noise down. =A0It is not
> just a matter of adding a high frequency capacitor to the power rail,
> it acts as a very low impedance transmission line connecting the
> capacitors to the power pins of the chip. =A0It is counter intuitive,
> but it actually is not so important to keep the caps so close to the
> chip if you are using good power planes. =A0BTW, to maximize the
> effectiveness of the power planes (read that as minimum impedance) you
> want to have the power and ground plane as close together as
> possible. =A05 mils spacing should be practical and will go a long way
> to doing a good job.
>
> I found doing layout to be fun, but very intense! =A0Most design
> requires you to go back and forth between specs and data sheets and
> the schematic capture package. =A0Layout has some up front work getting
> all the inputs and making the footprints, but then it just becomes a
> really complex rubics cube with many possible solutions. =A0Your job is
> to find one that is pretty good without spending tons of time on it.
>
> When I did my first layout, I contacted a couple of colleges and asked
> them to do a design review with me. =A0I was willing to pay them
> consulting rates, but I was turned down. =A0It turned out ok in the end,
> but there were a couple of things that likely would have been caught
> in a review. =A0I am not very busy right now. =A0If you would like and
> when you are ready, I'd be willing to go through a design review with
> you without charge. =A0I'm pretty bored and would enjoy it.
>
> Rick

Rick, thanks for all the help, and I appreciate the offer! I might
take you up on it. If you send me an e-mail to the address displayed
here, I can reply with a more useful e-mail address.. I use a kind of
junk-ish secondary address to access google groups because of all the
spam. I'd like not to be on google groups but I don't have a news
server at the moment, and don't know where to go for one..
I have some other things to do (including programming and testing the
first iteration on an already made dev board) so it's going to be a
little while before my layout is ready to go.

I have some reasons why Virtex-II and not something newer, and why
SRAM and all that, and there is a little bit more to the overall
system than I've mentioned though.

As for remapping the EEPROM, I'm not too worried about that because I
was going to whip up a second FPGA configuration just to write the
contents of the EEPROM, so the addresses and bit orders will come out
the same. But yeah I'd rather keep all the address lines as they are.

I probably won't be pushing timing to the max.. the critical thing is
that I can write continuously to RAM on a ~25MHz clock (or maybe I can
afford to go with half that) for a certain period.

Steve

> Now that I think of it, I suppose I could make the bus connection job
> a little simpler if I take advantage of the fact that RAM is "random
> access," so the address/data line numbers from chip to chip don't
> necessarily have to match up. Then the address/data lines could be
> connected in whatever order is easiest and cleanest, since on the FPGA
> side the data would go in and come out in the desired order either
> way.
> Would this for any reason be a bad design practice?


Cypress don't even define address and data pin numbers for their synchronous
rams (apart from A0 and A1).

Go for it.


Nial 

> John,
> I don't think I can get away with only the outer two rows of balls,
> I'll probably need the two inside of that as well-- I was thinking of
> breaking out the outer two on one signal layer and the inner two in
> another, as suggested in the Xilinx app note I saw. It was a tight
> squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
> is the standard offering of the board house we're using.. it's
> possible to ask for smaller, for an extra chunk of change.

With 1mm ball pitch I use 0.5mm pads, 0.5mm vias with 0.25mm drills.

This is pretty much run of the mill for fab houses and shouldn't
add much to costs.

The first four balls can then be routed out on the top and bottom
layers.

Nial 

On 2/5/2010 5:40 AM, rickman wrote:
>>
>> To the OP, in the absence of micro-vias, I would recommend a 6 layer
>> board. Maybe like this:-
>>
>> signal
>> signal
>> ground
>> ground
>> power/signal
>> signal
>>
>
> Everyone has their own way of doing things, but I would ask, why the
> two ground planes?  I would have a ground plane and a power plane in
> the center with a minimum thickness between them.  The spacing between
> the ground/power plane and the signal plane is not so important.  What
> is important is the characteristic impedance.  The lower the
> impedance, the less it will radiate.  Of course, with thin traces you
> have to have the signal plane to power/ground plane very small to get
> a low impedance.  But if you have wide traces, you can open up the
> plane spacing.  Since the outer layers are on the outside of the
> board, they won't be very close to inside power/ground planes.  BTW,
> you are aware that the power plane is just as effective as the ground
> plane for determining the impedance.
>
> Rick

Hi Rick,

In my designs, and perhaps yours too, the power plane, such as it is, is 
useless as a reference plane for the simple reason that it's chopped up 
into many different pours for all the different voltages. I don't think 
you are suggesting a separate layer for each separate voltage? So, there 
will be slots in the plane, and every time a fast signal passes across 
this slot, you'll get the thing radiating as a good slot antenna does! 
You could add a bunch of bypass caps to bridge between the planes, but 
there's rarely space for this with a dense BGA design. For sure, if your 
planes are close together in the middle of your stack, this problem is 
small, but then you need wider surface traces to get the impedance you 
require.
So, I recommend multiple ground planes close to all your signals. A 
thick core in the centre of the board to make up the correct thickness. 
Then you can simply forget about any slot issues. Like you say, this 
lets you keep the traces thin and with a lower characteristic impedance, 
which is normally what you want when routing BGA FPGAs. The two ground 
planes should be well bonded with vias, so there isn't a problem when a 
signal goes through a via and passes from being referred to one ground 
plane to the other.

I reject the notion of placing a power plane and a ground plane close 
together in the middle of the board to get the benefit of the 
inter-plane capacitance for bypassing reasons. Don't get me wrong, it 
won't hurt, but IMO the amount of capacitance gained is tiny, and even 
though it is a very high Q capacitor, getting the power to the die is 
stymied by the inductance of the vias and BGA balls that are part of the 
PDS. If your power plane is in the middle of the board, the signal path 
of these vias are longer. You don't care about the supply stiffness on 
your plane, it's on the die that counts. If you graunch off the metal 
cover of an FPGA you'll see that the manufacturer has already had to add 
bypass caps on the BGA substrate for this very reason. Furthermore, if 
you have a PCB ground plane close to the surface and hence close to the 
FPGA, the cavity between the PCB ground plane and the ground plane in 
the FPGA is smaller, reducing the inductance of the vias and BGA balls 
and so reducing stuff like ground bounce.
So, IMO, the disadvantages of having the planes further from your 
signals and components more than outweigh the tiny gain in bypass 
capacitance you gain.

I say better is to put your bypass caps as close as possible to the 
FPGA, and maybe use puddles of copper close to the ground planes to 
maximise the via and capacitor utilization. Here's an article showing 
what I mean. Fig. 2.

http://www.x2y.com/bypass/mount/backside_cap.pdf

Whatever, YMMV, and I'm sure your designs work just fine. It's hard to 
cock it up, but I contend that the dual ground plane design I suggest 
above is nigh on impossible to go wrong with from an SI point of view, 
even if you have absolutely no clue what you're doing. That's why I use it!

Cheers, Syms.