Board layout for FPGA

rickman <gnuarm@gmail.com> writes:

> BTW, you are aware that the power plane is just as effective as the
> ground plane for determining the impedance.

Yes, but the OP needs to be aware that care can be required when
switching your signal trace from one layer to another. When you switch
to a layer which references the other supply rail, then the return
current has to also switch layers.  If the way it has to do that is
via a decoupling cap a long way away then the current loop can be
quite large.  

I got Henry Ott's new book just this morning, and he has some
discussion on p630...  If you use Amazon's "search in this book"
feature from here:

http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/

and search for "Changing Reference Planes", you can see pp 630-631.

To the OP - ...and then buy it :)

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

On 2/5/2010 11:48 AM, Martin Thompson wrote:
> rickman<gnuarm@gmail.com>  writes:
>
>> BTW, you are aware that the power plane is just as effective as the
>> ground plane for determining the impedance.
>
> Yes, but the OP needs to be aware that care can be required when
> switching your signal trace from one layer to another. When you switch
> to a layer which references the other supply rail, then the return
> current has to also switch layers.  If the way it has to do that is
> via a decoupling cap a long way away then the current loop can be
> quite large.
>
> I got Henry Ott's new book just this morning, and he has some
> discussion on p630...  If you use Amazon's "search in this book"
> feature from here:
>
> http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Henry-Ott/dp/0470189304/
>
> and search for "Changing Reference Planes", you can see pp 630-631.
>
> To the OP - ...and then buy it :)
>
> Cheers,
> Martin
>
Hi Martin,

It would appear Mr. Ott agrees that multiple ground planes with a big 
centre core are a good idea, even on a four layer board. Fig. 16-15. He 
must be a smart guy!! ;-)

Also, Fig. 16-16 he specifically says that

signal
signal
ground
power
signal
signal

is _not_ recommended.


Looks like he would do

signal
ground
signal
signal
ground
signal

with a thick centre core and routed powers. This way the internal signal 
layers are shielded. I tend to agree. The ssggss stack I suggested 
because I almost always use laser drilled micro-vias on my boards, so I 
need two signal layers on the outside. Also, my enclosures do the EMC 
shielding. With standard vias, sgssgs is probably better.

Cheers, Syms.

On Feb 5, 5:15=A0am, "Nial Stewart"
<nial*REMOVE_TH...@nialstewartdevelopments.co.uk> wrote:
> > John,
> > I don't think I can get away with only the outer two rows of balls,
> > I'll probably need the two inside of that as well-- I was thinking of
> > breaking out the outer two on one signal layer and the inner two in
> > another, as suggested in the Xilinx app note I saw. It was a tight
> > squeeze but they wrote .127mm traces, and .3/.6mm on the vias, which
> > is the standard offering of the board house we're using.. it's
> > possible to ask for smaller, for an extra chunk of change.
>
> With 1mm ball pitch I use 0.5mm pads, 0.5mm vias with 0.25mm drills.
>
> This is pretty much run of the mill for fab houses and shouldn't
> add much to costs.

0.25 mm drill is 10 mil.  I have had fab houses say they can't do 10
mil.  One in particular applied a "standard" rule of +- 3 mil
tolerance and used a 13 mil drill without telling me.  Of course,
without saying any names, I don't use Sunstone anymore.  ;^)  (They
also had a >20% Xout rate on that run and had to do a second run to
get me the last panel, not that I would ever bad mouth them...)

The lower limit for the lower end board houses (in terms of costs not
quality) tends to be around 15 mil.  I don't think you can do any of
these BGAs using 15 mil vias, so the truly low end houses are likely
out anyway.  It is important to choose a *good* fab house.  I have
found quality to vary a *lot*.

Rick

> The lower limit for the lower end board houses (in terms of costs not
> quality) tends to be around 15 mil.  I don't think you can do any of
> these BGAs using 15 mil vias, so the truly low end houses are likely
> out anyway.  It is important to choose a *good* fab house.  I have
> found quality to vary a *lot*.


Aye, I'd assumed a 'proper' board house, not a pile em high outfit like
PCB pool etc (although I've always had good results using pcb pool for lower
tech boards).


Nial. 

On Feb 5, 8:45 am, Symon <symon_bre...@hotmail.com> wrote:
> On 2/5/2010 11:48 AM, Martin Thompson wrote:
>
> > rickman<gnu...@gmail.com>  writes:
>
> >> BTW, you are aware that the power plane is just as effective as the
> >> ground plane for determining the impedance.
>
> > Yes, but the OP needs to be aware that care can be required when
> > switching your signal trace from one layer to another. When you switch
> > to a layer which references the other supply rail, then the return
> > current has to also switch layers.  If the way it has to do that is
> > via a decoupling cap a long way away then the current loop can be
> > quite large.
>
> > I got Henry Ott's new book just this morning, and he has some
> > discussion on p630...  If you use Amazon's "search in this book"
> > feature from here:
>
> >http://www.amazon.co.uk/Electromagnetic-Compatibility-Engineering-Hen...
>
> > and search for "Changing Reference Planes", you can see pp 630-631.
>
> > To the OP - ...and then buy it :)
>
> > Cheers,
> > Martin
>
> Hi Martin,
>
> It would appear Mr. Ott agrees that multiple ground planes with a big
> centre core are a good idea, even on a four layer board. Fig. 16-15. He
> must be a smart guy!! ;-)
>
> Also, Fig. 16-16 he specifically says that
>
> signal
> signal
> ground
> power
> signal
> signal
>
> is _not_ recommended.
>
> Looks like he would do
>
> signal
> ground
> signal
> signal
> ground
> signal
>
> with a thick centre core and routed powers. This way the internal signal
> layers are shielded. I tend to agree. The ssggss stack I suggested
> because I almost always use laser drilled micro-vias on my boards, so I
> need two signal layers on the outside. Also, my enclosures do the EMC
> shielding. With standard vias, sgssgs is probably better.
>
> Cheers, Syms.

In reply to both of your posts, I will say that there is a *lot* of
misinformation out there.  There is *NO* one way to stack up PCBs.  I
once took a class in "High Speed Digital Design" with Lee Ritchey.
Some "experts" in the field will explain the theory behind what they
say.  Lee Ritchey not only gives the theory, he also shows detail
simulations and even builds test boards to verify that what he is
saying is how it works in the real world.  That impressed me
greatly.

As to the return current having to "jump" between layers being a
problem, if you use the ssgpss stackup and have the power and ground
very close rather than widely spaced, the capacitive coupling allows
the signal to switch between them without issue.  In fact, when
splitting a plane for multiple power sections, the return current will
switch from one power plane, to the ground plane and back to the next
power plane as if they were all one plane.  This is because of the
capacitive coupling between layers.  Of course this only works for the
highest frequency components of the signals, but that's all we really
care about, no?

-------+  +-------> Return Current
=======|  |======== Power Planes
       |  |
       +--+
=================== Ground Plane

The ascii art may not come out too well depending on your browser or
newreader, but I hope you get the idea.

I couldn't view the pages in Ott's book so I can't respond to that.
The one point I most learned from Lee Ritchey's course is that you
should never take any expert's opinion as fact.  Many experts make
mistakes and a number of things look good on paper while the real
world works differently.  Only trust an expert opinion if it is backed
up by reliable proof.  How does Ott "prove" his analysis, or is it
just a paper analysis?

Rick

On Feb 5, 6:42 am, Symon <symon_bre...@hotmail.com> wrote:
> On 2/5/2010 5:40 AM, rickman wrote:
>
> >> To the OP, in the absence of micro-vias, I would recommend a 6 layer
> >> board. Maybe like this:-
>
> >> signal
> >> signal
> >> ground
> >> ground
> >> power/signal
> >> signal
>
> > Everyone has their own way of doing things, but I would ask, why the
> > two ground planes?  I would have a ground plane and a power plane in
> > the center with a minimum thickness between them.  The spacing between
> > the ground/power plane and the signal plane is not so important.  What
> > is important is the characteristic impedance.  The lower the
> > impedance, the less it will radiate.  Of course, with thin traces you
> > have to have the signal plane to power/ground plane very small to get
> > a low impedance.  But if you have wide traces, you can open up the
> > plane spacing.  Since the outer layers are on the outside of the
> > board, they won't be very close to inside power/ground planes.  BTW,
> > you are aware that the power plane is just as effective as the ground
> > plane for determining the impedance.
>
> > Rick
>
> Hi Rick,
>
> In my designs, and perhaps yours too, the power plane, such as it is, is
> useless as a reference plane for the simple reason that it's chopped up
> into many different pours for all the different voltages. I don't think
> you are suggesting a separate layer for each separate voltage? So, there
> will be slots in the plane, and every time a fast signal passes across
> this slot, you'll get the thing radiating as a good slot antenna does!
> You could add a bunch of bypass caps to bridge between the planes, but
> there's rarely space for this with a dense BGA design. For sure, if your
> planes are close together in the middle of your stack, this problem is
> small, but then you need wider surface traces to get the impedance you
> require.
> So, I recommend multiple ground planes close to all your signals. A
> thick core in the centre of the board to make up the correct thickness.
> Then you can simply forget about any slot issues. Like you say, this
> lets you keep the traces thin and with a lower characteristic impedance,
> which is normally what you want when routing BGA FPGAs. The two ground
> planes should be well bonded with vias, so there isn't a problem when a
> signal goes through a via and passes from being referred to one ground
> plane to the other.

Below, you talk about the connecting of the power and ground plane by
spacing to be of little value and yet propose that vias are adequate
to couple multiple ground planes.  I find that interesting.  For a
signal passing between layers the return current would have a long
path to reach a via and back.


> I reject the notion of placing a power plane and a ground plane close
> together in the middle of the board to get the benefit of the
> inter-plane capacitance for bypassing reasons. Don't get me wrong, it
> won't hurt, but IMO the amount of capacitance gained is tiny, and even
> though it is a very high Q capacitor, getting the power to the die is
> stymied by the inductance of the vias and BGA balls that are part of the
> PDS. If your power plane is in the middle of the board, the signal path
> of these vias are longer. You don't care about the supply stiffness on
> your plane, it's on the die that counts. If you graunch off the metal
> cover of an FPGA you'll see that the manufacturer has already had to add
> bypass caps on the BGA substrate for this very reason. Furthermore, if
> you have a PCB ground plane close to the surface and hence close to the
> FPGA, the cavity between the PCB ground plane and the ground plane in
> the FPGA is smaller, reducing the inductance of the vias and BGA balls
> and so reducing stuff like ground bounce.
> So, IMO, the disadvantages of having the planes further from your
> signals and components more than outweigh the tiny gain in bypass
> capacitance you gain.

I'm a bit unclear on what you are saying.  You are suggesting that the
impedance of the vias is enough that you should put the planes as
close as possible to the component surface, but then you recommend
putting the decoupling caps on the back side much further away from
the component with longer vias.


> I say better is to put your bypass caps as close as possible to the
> FPGA, and maybe use puddles of copper close to the ground planes to
> maximise the via and capacitor utilization. Here's an article showing
> what I mean. Fig. 2.
>
> http://www.x2y.com/bypass/mount/backside_cap.pdf
>
> Whatever, YMMV, and I'm sure your designs work just fine. It's hard to
> cock it up, but I contend that the dual ground plane design I suggest
> above is nigh on impossible to go wrong with from an SI point of view,
> even if you have absolutely no clue what you're doing. That's why I use it!
>
> Cheers, Syms.


Yes, one common element is that most designs apply overkill in the
supply decoupling area.  When an engineer uses a method and it works,
it is like the elephant protection charm... you don't see any
elephants do you, so it must be working!

I would likely not use the offset coupled planes you describe mainly
because it only works well for boards with active components on only
one side.

In Lee Ritchey's class I asked about adding caps to the package to
overcome lead inductance causing ground bounce.  He showed me that the
bounce is caused by the switching currents of driving an external
signal travel in a loop and independent of any capacitance on the
package, still have to travel through the leads of the part (even if
they are only bonding leads).  In fact, there is *nothing* you can do
about the series inductance of pins in a package other than fix the
package.  That is why I seriously doubt that the small added
inductance of 30 mil of a via is significant in any but the highest
speed designs.  But as you say, YMMV.

Rick

>Yes, one common element is that most designs apply overkill in the
>supply decoupling area.  When an engineer uses a method and it works,
>it is like the elephant protection charm... you don't see any
>elephants do you, so it must be working!

Just for amusement, I tried an experiment on a simple FPGA board I designed recently -board has a
Lattice EC3, driving a small TFT LCD from video data in NAND flash.
It's a 2 layer PCB, with about ten 100n decouplers wherever space allowed and a couple of 1u
ceramics on each rail. 
I removed ALL the decouplers apart from a single 1u on each rail to keep the LDOs happy. Board still
worked just fine..... didn't do any noise measurements though....

A few years ago I saw a very amusing talk at London Dorkbot - in an attempt to bring old board games
up to date, James Larson created "Motherboard Operation" - players take it in turns to snip
components from a working, running PC motherboard until it stops working...
This was accompanied by "PC PSU Buckaroo" - players choose and add more and more loads to an old PC
power supply until it fails.... 
 

On 2/5/2010 7:15 PM, Mike Harrison wrote:
> worked just fine..... didn't do any noise measurements though....
>
> A few years ago I saw a very amusing talk at London Dorkbot - in an attempt to bring old board games
> up to date, James Larson created "Motherboard Operation" - players take it in turns to snip
> components from a working, running PC motherboard until it stops working...
>
That's like Muntzing! Named after Madman Muntz. :-)

(comp.dsp added, as there are people there who consider these problems.)

rickman <gnuarm@gmail.com> wrote:
> On Feb 5, 6:42 am, Symon <symon_bre...@hotmail.com> wrote:
(snip)

>> In my designs, and perhaps yours too, the power plane, such as it is, is
>> useless as a reference plane for the simple reason that it's chopped up
>> into many different pours for all the different voltages. I don't think
>> you are suggesting a separate layer for each separate voltage? So, there
>> will be slots in the plane, and every time a fast signal passes across
>> this slot, you'll get the thing radiating as a good slot antenna does!
>> You could add a bunch of bypass caps to bridge between the planes, but
>> there's rarely space for this with a dense BGA design. For sure, if your
>> planes are close together in the middle of your stack, this problem is
>> small, but then you need wider surface traces to get the impedance you
>> require.

It is not at all easy to figure out the impedance of ground 
(or power) planes.  There have been long discussions, either here
or in other groups, about signals crossing slots between planes.
I believe that it isn't as simple as you say, but one should still
be careful about it.

>> So, I recommend multiple ground planes close to all your signals. A
>> thick core in the centre of the board to make up the correct thickness.
>> Then you can simply forget about any slot issues. Like you say, this
>> lets you keep the traces thin and with a lower characteristic impedance,
>> which is normally what you want when routing BGA FPGAs. The two ground
>> planes should be well bonded with vias, so there isn't a problem when a
>> signal goes through a via and passes from being referred to one ground
>> plane to the other.
 
> Below, you talk about the connecting of the power and ground plane by
> spacing to be of little value and yet propose that vias are adequate
> to couple multiple ground planes.  I find that interesting.  For a
> signal passing between layers the return current would have a long
> path to reach a via and back.

I believe, for the most part, it doesn't do that.  The capacitance
of even a single plane is high enough at the higher frequencies
that for the most part the return current doesn't have to take
the long way around.  
 
>> I reject the notion of placing a power plane and a ground plane close
>> together in the middle of the board to get the benefit of the
>> inter-plane capacitance for bypassing reasons. Don't get me wrong, it
>> won't hurt, but IMO the amount of capacitance gained is tiny, and even
>> though it is a very high Q capacitor, getting the power to the die is
>> stymied by the inductance of the vias and BGA balls that are part of the
>> PDS. 

I think I agree with this.  The way to actually see this is to
calculate the radial propagation of the signal into the plane 
from the via.  The impedance (both inductance and capacitance)
will change with radial distance and frequency.  

>> If your power plane is in the middle of the board, the signal path
>> of these vias are longer. You don't care about the supply stiffness on
>> your plane, it's on the die that counts. 

Well, I think it is both.  For a single supply via, yes.  But if you
add them all up, then the ground plane has to supply (or sink) the
total of all the vias, and some of that comes from the interplane
capacitance.  The via inductance will be most important at the
highest frequencies.  The ground plane at slightly lower, but 
still significant frequencies.  At some point there is a tradeoff
between the two, and you have to figure out what that means in terms
of plane positioning.

>> If you graunch off the metal
>> cover of an FPGA you'll see that the manufacturer has already had to add
>> bypass caps on the BGA substrate for this very reason. Furthermore, if
>> you have a PCB ground plane close to the surface and hence close to the
>> FPGA, the cavity between the PCB ground plane and the ground plane in
>> the FPGA is smaller, reducing the inductance of the vias and BGA balls
>> and so reducing stuff like ground bounce.
>> So, IMO, the disadvantages of having the planes further from your
>> signals and components more than outweigh the tiny gain in bypass
>> capacitance you gain.
 
> I'm a bit unclear on what you are saying.  You are suggesting that the
> impedance of the vias is enough that you should put the planes as
> close as possible to the component surface, but then you recommend
> putting the decoupling caps on the back side much further away from
> the component with longer vias.

To see this, you have to think of it in frequency (Fourier) space.
The switching currents have frequency components over a wide 
range, with a peak somewhere near 1/(transition time) but 
significant over a range of lower frequencies.  The highest ones
are supplied by the internal capacitors.  The next lower ones
by the ground plane itself, near the via.  Lower still by the
ground plane farther away, where interplane capacitance is important. 
Then there are the onboard bypass capacitors, the power supply
bypass capacitors, the power supply filter capacitors, etc.
 
>> I say better is to put your bypass caps as close as possible to the
>> FPGA, and maybe use puddles of copper close to the ground planes to
>> maximise the via and capacitor utilization. Here's an article showing
>> what I mean. Fig. 2.

>> http://www.x2y.com/bypass/mount/backside_cap.pdf

>> Whatever, YMMV, and I'm sure your designs work just fine. It's hard to
>> cock it up, but I contend that the dual ground plane design I suggest
>> above is nigh on impossible to go wrong with from an SI point of view,
>> even if you have absolutely no clue what you're doing. That's why I use it!
 
> Yes, one common element is that most designs apply overkill in the
> supply decoupling area.  When an engineer uses a method and it works,
> it is like the elephant protection charm... you don't see any
> elephants do you, so it must be working!
 
> I would likely not use the offset coupled planes you describe mainly
> because it only works well for boards with active components on only
> one side.
 
> In Lee Ritchey's class I asked about adding caps to the package to
> overcome lead inductance causing ground bounce.  He showed me that the
> bounce is caused by the switching currents of driving an external
> signal travel in a loop and independent of any capacitance on the
> package, still have to travel through the leads of the part (even if
> they are only bonding leads).  In fact, there is *nothing* you can do
> about the series inductance of pins in a package other than fix the
> package.  That is why I seriously doubt that the small added
> inductance of 30 mil of a via is significant in any but the highest
> speed designs.  But as you say, YMMV.

Yes.  The problem comes with switching a large number of lines
at very close to the same time.  Since they won't be at exactly
the same time (propagation delay to the pads) the highest frequency
components aren't as important as you might think.  The peak
frequency of the ground current, then, will depend on how close
the transitions are to each other more than the transition rate.

Now, consider writing zero to a 64 bit data bus.  All drivers
going low on the same clock cycle!

-- glen

Mike Harrison <mike@whitewing.co.uk> wrote:

(snip)

> up to date, James Larson created "Motherboard Operation" - players 
> take it in turns to snip components from a working, running PC 
> motherboard until it stops working...  

> This was accompanied by "PC PSU Buckaroo" - players choose and add 
> more and more loads to an old PC power supply until it fails.... 

I haven't tried it recently, but it used to be that PC power
supplies would fail at zero load.  I did it once (I don't remember
why) and smoked one.  (Yes, real smoke.)  

The original PC/AT had an optional hard disk drive.  If you didn't
buy one there was a load resistor on the power supply to meet the
minimum load requirement.  You would think that the AT motherboard
would take enough current, but it seems not.

-- glen