Board layout for FPGA

In comp.arch.fpga rickman <gnuarm@gmail.com> wrote:
(snip)
 
> My bad here.  I am the one saying that the planes will capacitively
> couple and allow the return current to cross slots in one plane by
> jumping to the other.  I got your post mixed up with Symon's post
> where he recommends multiple ground planes stitched together with vias
> rather than capacitively coupled power/ground planes.

Well, you want it to stay low impedance all the way down to DC.
 
>> (snip, I wrote)

>> I completely agree. ?Well, actually computers are probably about
>> fast enough to do the whole calculation for at least one board trace
>> using the actual geometry. ?With linearity you can compute each one
>> and add them together. ?

>> > Lee has done that. ?One test he made
>> > that really impressed me was to show that a decoupling cap does not
>> > need to be close to a pin to work well. ?If the power and ground plane
>> > are closely spaced, the impedance is very low. ?If you understand
>> > transmission lines, you will know that the current into (or out of) a
>> > driver into the transmission line is constant until the signal reaches
>> > the other end and depending on what load it finds, either continues
>> > until the reflection returns to the driver (as in a series terminated
>> > line with high impedance load) or keeps flowing as when it reaches the
>> > decoupling cap. ?

>> Well, it has the impedance of the transmission line itself.
>> That depends on the inductance and capacitance of the conductors
>> making up the transmission line. ?You can consider a linear
>> transmission line as a sequence of series inductors and parallel
>> capacitors of constant value per unit length. ?Consider the
>> impedance of a finite length open ended transmission line as
>> a function of frequency. ?For some frequencies the impedance will
>> be very low, for others it will be very high. ?This property
>> is used for impedance matching and filtering in RF circuits.
 
> I am aware of what a transmission line is.  That is my point.  The
> transmission line of closely spaced planes is a very low impedance
> which supplies current for the full time it takes the impulse to reach
> the cap.  So the spacing of the caps is not at all critical contrary
> to what many will tell you.

I believe, though, that radial transmission lines aren't 
discussed much in classes.  I hadn't thought of them much until
I was replying to your post.  A google search for them brought
up the paper that I tried to reference.  I did the search on a 
different computer and copied the link by hand.  I will try again.

(Interesting all the ads that come for towing companies and
transmission repair.)
 
(snip)
>> Now, consider the case of a signal going into or out of a supply
>> plane. ?Now instead of the constant inductance and capacitance
>> per unit length you have concentric rings. ?The inductance decreases
>> and the capacitance increase with radial distance. ?In transmission
>> line terms, it is a line with the impedance decreasing with R.
>> Impedance decreases pretty fast, too. ?

>> A quick web search finds a paper that looks interesting on just
>> this problem. ?

>> http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf

>> The paper has much more detail than even I know, and includes
>> comparisons of calculations and actual boards.
 
> What paper?  I get a 404 error, page not found.  Still, I don't see
> the problem you seem to be describing.  So the impedance drops with
> increasing distance, low impedance in the power supply is a good
> thing, no?  Why would it dropping be a bad thing?

OK, try again.

   http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf

he seems to even include the reflections of other vias, which
seems more than is needed to me, but...

It looks like the other papers on on slot antenna design,
so he is considering PC board design in slot antenna terms.
 
> Lee actually has impedance vs. frequency measurements of power/ground
> planes and it is pretty interesting.  They don't do much below 100 MHz
> or so, but beyond that the impedance is an up/down trace (all
> adequately low) until it finally starts to climb above several GHz.
> IIRC he explained the the sawtooth as having to do with the board
> dimensions.  I guess it has something to do with standing waves, but
> it was some four years ago and I don't recall for sure.

With some bad luck you might get a resonance (standing wave)
where the impedance didn't stay low.
 
> I do remember that he showed some interesting interactions between the
> plane capacitance and the inductance of the small sized and valued
> decoupling caps.  They have a resonance around 100-200 MHz I think,
> which drives the impedance way up at that value.  His solution was to
> add other value caps which effectively move that resonance and also
> damp it out to where it is acceptable.  I think he showed a board
> where he used a total of three different values of ceramic caps, but
> only a small number of each, to get a very quiet board with a very
> constant power delivery system impedance.  When I took the course, I
> understood how to figure it all out, but I have not had a design with
> difficult power decoupling needs, so I have forgotten some of it.
> Good thing I still have the book... somewhere...

In the old days, it might be that the tolerance kept the resonances
from being too close.  The uniformity is so good now that they
will all have resonance too close together.
 
(snip)
> So the physics of each board is different???  The board Lee
> constructed was a test board.  I don't recall what he used for a
> source of the transient, but he had spots for capacitors at a minimum
> of three distances connected to the power/ground planes with optimally
> short runs to the vias.  He populated the caps one at a time and
> measured the effectiveness finding that it dropped off barely at all
> at an inch, IIRC and only moderately at a couple or three inches.  The
> point is that it is not really needed to put the cap right on top of
> the power pin.  A good power/ground plane pair is much more
> important.
 
(snip) 
> My point is that this is all theory.  Unless you take some
> measurements to verify what you are saying, you can't say it is an
> accurate description of a real board and chip.  Also consider that one
> via is not a power supply.  Vias are used in parallel giving an
> effectively low impedance.

Hopefully the link is right now.  He does both theory and measurement.

-- glen

Symon <symon_brewer@hotmail.com> wrote:
> On 2/6/2010 8:13 AM, rickman wrote:
>>   To be honest, I don't know
>> why they would put caps inside the package
 
> The caps are on the package because the inductance of the connecting 
> vias and package balls means that, no matter how good the bypassing is 
> on the PCB, the die on the package will have bypassing problems with 
> it's supply. This is why I believe the high Q bypassing from a power 
> plane and a ground plane doesn't help, and the layers can be arranged 
> differently to achieve better results by optimising other areas.

I think what he means is that the resonance will still be too
low even inside the package.  

-- glen

On 2/6/2010 7:04 PM, glen herrmannsfeldt wrote:
> Symon<symon_brewer@hotmail.com>  wrote:
>> On 2/6/2010 8:13 AM, rickman wrote:
>>>    To be honest, I don't know
>>> why they would put caps inside the package
>
>> The caps are on the package because the inductance of the connecting
>> vias and package balls means that, no matter how good the bypassing is
>> on the PCB, the die on the package will have bypassing problems with
>> it's supply. This is why I believe the high Q bypassing from a power
>> plane and a ground plane doesn't help, and the layers can be arranged
>> differently to achieve better results by optimising other areas.
>
> I think what he means is that the resonance will still be too
> low even inside the package.
>
> -- glen


What resonance?

On 2/6/2010 5:38 PM, rickman wrote:
>
> I keep asking you if you have done any real analysis or measurements
> of what you are stating?
 >

Well, this was the first time you asked IIRC, but thank you for doing 
so. The answer is "For sure". I've used Hyperlynx and Spice on my 
boards. I guess you have also, or else you would not be able to post 
your opinions without worrying you might giving someone a bum steer.

> I am no guru,

Really?

 >
> but I was *very* impressed by
> what Lee Ritchey said just because he has full support for just about
> everything he stated in his course (except maybe that the food was
> good at the Chinese restaurant).
>
> Rick

You seem to be _very_ impressed. Almost as impressed as Steve Wier.

http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4

On 2/6/2010 6:15 PM, rickman wrote:
>> will increase with frequency.
>
> My point is that this is all theory.  Unless you take some
> measurements to verify what you are saying, you can't say it is an
> accurate description of a real board and chip.  Also consider that one
> via is not a power supply.  Vias are used in parallel giving an
> effectively low impedance.
>
> Rick

Rick,
Do you measure every resistor you put on a board. Ohm's law is a theory, 
after all.
Syms xx

Symon <symon_brewer@hotmail.com> wrote:

(snip on bypass capacitors)
 
> What resonance?

The limit to the useful frequency range of a capacitor is
when it reaches resonance with the series (lead, package, etc.)
inductance.    Graph impedance vs. frequency, when the reactive
component crosses zero that it resonance.

-- glen

On 2/7/2010 1:03 AM, glen herrmannsfeldt wrote:
> Symon<symon_brewer@hotmail.com>  wrote:
>
> (snip on bypass capacitors)
>
>> What resonance?
>
> The limit to the useful frequency range of a capacitor is
> when it reaches resonance with the series (lead, package, etc.)
> inductance.    Graph impedance vs. frequency, when the reactive
> component crosses zero that it resonance.
>
> -- glen

Hi Glen,
Are you sure? Even beyond that frequency the cap is still doing 
something, isn't it?
Syms.

On Feb 6, 2:01=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> In comp.arch.fpga rickman <gnu...@gmail.com> wrote:
> (snip)
>
> > My bad here. =A0I am the one saying that the planes will capacitively
> > couple and allow the return current to cross slots in one plane by
> > jumping to the other. =A0I got your post mixed up with Symon's post
> > where he recommends multiple ground planes stitched together with vias
> > rather than capacitively coupled power/ground planes.
>
> Well, you want it to stay low impedance all the way down to DC.

I don't get how this comment relates to the above.


> >> (snip, I wrote)
> >> I completely agree. ?Well, actually computers are probably about
> >> fast enough to do the whole calculation for at least one board trace
> >> using the actual geometry. ?With linearity you can compute each one
> >> and add them together. ?
> >> > Lee has done that. ?One test he made
> >> > that really impressed me was to show that a decoupling cap does not
> >> > need to be close to a pin to work well. ?If the power and ground pla=
ne
> >> > are closely spaced, the impedance is very low. ?If you understand
> >> > transmission lines, you will know that the current into (or out of) =
a
> >> > driver into the transmission line is constant until the signal reach=
es
> >> > the other end and depending on what load it finds, either continues
> >> > until the reflection returns to the driver (as in a series terminate=
d
> >> > line with high impedance load) or keeps flowing as when it reaches t=
he
> >> > decoupling cap. ?
> >> Well, it has the impedance of the transmission line itself.
> >> That depends on the inductance and capacitance of the conductors
> >> making up the transmission line. ?You can consider a linear
> >> transmission line as a sequence of series inductors and parallel
> >> capacitors of constant value per unit length. ?Consider the
> >> impedance of a finite length open ended transmission line as
> >> a function of frequency. ?For some frequencies the impedance will
> >> be very low, for others it will be very high. ?This property
> >> is used for impedance matching and filtering in RF circuits.
> > I am aware of what a transmission line is. =A0That is my point. =A0The
> > transmission line of closely spaced planes is a very low impedance
> > which supplies current for the full time it takes the impulse to reach
> > the cap. =A0So the spacing of the caps is not at all critical contrary
> > to what many will tell you.
>
> I believe, though, that radial transmission lines aren't
> discussed much in classes. =A0I hadn't thought of them much until
> I was replying to your post. =A0A google search for them brought
> up the paper that I tried to reference. =A0I did the search on a
> different computer and copied the link by hand. =A0I will try again.

The point is that they work very well for power decoupling.  The main
point in designing them is to keep the spacing between the plates
small so that the capacitance is high and the impedance is low.


> >> Now, consider the case of a signal going into or out of a supply
> >> plane. ?Now instead of the constant inductance and capacitance
> >> per unit length you have concentric rings. ?The inductance decreases
> >> and the capacitance increase with radial distance. ?In transmission
> >> line terms, it is a line with the impedance decreasing with R.
> >> Impedance decreases pretty fast, too. ?
> >> A quick web search finds a paper that looks interesting on just
> >> this problem. ?
> >>http://www.waves.utoronto.ca/prof/gleefth/Backup_Old/jpub/6.pdf
> >> The paper has much more detail than even I know, and includes
> >> comparisons of calculations and actual boards.
> > What paper? =A0I get a 404 error, page not found. =A0Still, I don't see
> > the problem you seem to be describing. =A0So the impedance drops with
> > increasing distance, low impedance in the power supply is a good
> > thing, no? =A0Why would it dropping be a bad thing?
>
> OK, try again.
>
> =A0 =A0http://www.waves.utoronto.ca/prof/gelefth/Backup_Old/jpub/6.pdf

I still can't read it. 404 not found error again.


> he seems to even include the reflections of other vias, which
> seems more than is needed to me, but...
>
> It looks like the other papers on on slot antenna design,
> so he is considering PC board design in slot antenna terms.
>
> > Lee actually has impedance vs. frequency measurements of power/ground
> > planes and it is pretty interesting. =A0They don't do much below 100 MH=
z
> > or so, but beyond that the impedance is an up/down trace (all
> > adequately low) until it finally starts to climb above several GHz.
> > IIRC he explained the the sawtooth as having to do with the board
> > dimensions. =A0I guess it has something to do with standing waves, but
> > it was some four years ago and I don't recall for sure.
>
> With some bad luck you might get a resonance (standing wave)
> where the impedance didn't stay low.

Adding caps helps this in a couple of ways.  Each size cap has an
impedance min at different frequencies, but the fact that they are not
high Q and have ESR means they damp out the high peaks from
resonance.  It appears to work very well in Lee's measurements.


> > I do remember that he showed some interesting interactions between the
> > plane capacitance and the inductance of the small sized and valued
> > decoupling caps. =A0They have a resonance around 100-200 MHz I think,
> > which drives the impedance way up at that value. =A0His solution was to
> > add other value caps which effectively move that resonance and also
> > damp it out to where it is acceptable. =A0I think he showed a board
> > where he used a total of three different values of ceramic caps, but
> > only a small number of each, to get a very quiet board with a very
> > constant power delivery system impedance. =A0When I took the course, I
> > understood how to figure it all out, but I have not had a design with
> > difficult power decoupling needs, so I have forgotten some of it.
> > Good thing I still have the book... somewhere...
>
> In the old days, it might be that the tolerance kept the resonances
> from being too close. =A0The uniformity is so good now that they
> will all have resonance too close together.

It doesn't matter where the resonance is, the ESR keeps the peaks from
being very high and using multiple values makes the result pretty flat
or at least adequately low everywhere.


> > So the physics of each board is different??? =A0The board Lee
> > constructed was a test board. =A0I don't recall what he used for a
> > source of the transient, but he had spots for capacitors at a minimum
> > of three distances connected to the power/ground planes with optimally
> > short runs to the vias. =A0He populated the caps one at a time and
> > measured the effectiveness finding that it dropped off barely at all
> > at an inch, IIRC and only moderately at a couple or three inches. =A0Th=
e
> > point is that it is not really needed to put the cap right on top of
> > the power pin. =A0A good power/ground plane pair is much more
> > important.
>
> (snip)
>
> > My point is that this is all theory. =A0Unless you take some
> > measurements to verify what you are saying, you can't say it is an
> > accurate description of a real board and chip. =A0Also consider that on=
e
> > via is not a power supply. =A0Vias are used in parallel giving an
> > effectively low impedance.
>
> Hopefully the link is right now. =A0He does both theory and measurement.

I'll have to wait until another day.  BTW, does he actually relate
this to power supply decoupling or is this just a transmission line
analysis?

Rick

On Feb 6, 7:44=A0pm, Symon <symon_bre...@hotmail.com> wrote:
> On 2/6/2010 6:15 PM, rickman wrote:
>
> >> will increase with frequency.
>
> > My point is that this is all theory. =A0Unless you take some
> > measurements to verify what you are saying, you can't say it is an
> > accurate description of a real board and chip. =A0Also consider that on=
e
> > via is not a power supply. =A0Vias are used in parallel giving an
> > effectively low impedance.
>
> > Rick
>
> Rick,
> Do you measure every resistor you put on a board. Ohm's law is a theory,
> after all.
> Syms xx

I have measured a resistor's value before as well as the voltage and
current through it.  Then I knew that there was nothing amiss in the
circuit that I was not considering in my *theoretical* analysis of the
circuit.

Do you get the idea or are you still going to just arm chair
philosophize your power supply designs?

Rick

On Feb 6, 7:37=A0pm, Symon <symon_bre...@hotmail.com> wrote:
> On 2/6/2010 5:38 PM, rickman wrote:
>
> > I keep asking you if you have done any real analysis or measurements
> > of what you are stating?
>
> =A0>
>
> Well, this was the first time you asked IIRC, but thank you for doing
> so. The answer is "For sure". I've used Hyperlynx and Spice on my
> boards. I guess you have also, or else you would not be able to post
> your opinions without worrying you might giving someone a bum steer.

So are you going to share the results of these simulations on the vias
you are talking about?


> > I am no guru,
>
> Really?
>
> =A0>
>
> > but I was *very* impressed by
> > what Lee Ritchey said just because he has full support for just about
> > everything he stated in his course (except maybe that the food was
> > good at the Chinese restaurant).
>
> > Rick
>
> You seem to be _very_ impressed. Almost as impressed as Steve Wier.
>
> http://www.freelists.org/post/si-list/Lee-Ritcheys-book,4

I don't see anything that is a real criticism of Lee's ideas.  He is
critiquing the book and most of what he says are negative points are
actually editorial in nature.  He may not have all the background in
his book,, but everything he discussed in class was supported very
thoroughly.  I actually have not read the book in detail.  I use the
class handouts more I think.

Notice the reviewer's comment, "Chapters 32 - 37 on power distribution
issues are very good, with strong analysis, and practical solutions."
That is exactly the topic we are covering.

Rick

BTW, I am not trying to turn this into a pissing contest.  If you
don't like the way I am discussing this, I am happy to stop.