What is the basis on flip-flops replaced by a latch

On Feb 13, 1:01=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Feb 12, 7:35=A0pm, Patrick Maupin <pmau...@gmail.com> wrote:

> > On Feb 12, 10:32=A0am, rickman <gnu...@gmail.com> wrote:
>
> > > In the case of using latches in place of registers, the speed gains
> > > are always usable. =A0But can't the same sort of gains be made by
> > > register leveling? =A0If you have logic that is slower than a clock
> > > cycle followed by logic that is faster than a clock cycle, why not
> > > just move some of the slow logic across the register to the faster
> > > logic section?
>
> > That's a similar technique, to be sure, for speed-gains. =A0But as I
> > wrote in an earlier post, I think the primary motivation for latch-
> > based design was originally cost. =A0For example, since each flop is
> > really two latches, if you are going to have logic which ANDs together
> > the output of two flops, you could replace that with ANDing the output
> > of two latches, and outputting that result through another latch, for
> > a net savings of 75% of the latches.
>
> Your method's target and the target used by CPU designers inserting
> latches in the pipeline line are totally different.
>
> They use it because a combinational signal time delay is tool long to
> fit within one clock cycle and too short within two clock cycles in a
> pipeline, not in any places you may want to.

I was agreeing with rickman that in many cases, register retiming can
achieve similarly satisfactory results, while pointing out there were
originally other reasons besides timing to use latches.

I agree that latches are used for speed reasons, as well as cost
reasons.  But, as the paper you cite points out, the timing tools
aren't very good at analyzing the speed, and I don't know about the
specifics of the atom, but these days, if a chip designer wants
something that goes faster, he'll just as often use some domino logic
on a few paths rather than using simple latches -- same concept but
even more complicated.

In any case, you have to get your timing information somewhere -- a
latch really is just half a flop, and you have to decide when to close
it, so often you're either you're doing some fancy self-timing, or
your local clock tree gets a lot more complicated when you are doing
the described time-borrowing.

Regards,
Pat

On Feb 13, 6:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
> The description comes out a little muddy which is why it took me a few
> days to buy in to the whole concept. =A0It's sweet! =A0It just takes some
> timing diagrams and head scratching. =A0And it's certainly not set up
> for proper analysis especially in the Xilinx tools where I
> experimented with the phase domain changes.

It's not just FPGA tools.  Many of the high-end chip tools don't
support this very well, and to do it you need a PhD in the tool.

On Feb 14, 12:17=A0am, Patrick Maupin <pmau...@gmail.com> wrote:
> On Feb 13, 6:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
>
> > The description comes out a little muddy which is why it took me a few
> > days to buy in to the whole concept. =A0It's sweet! =A0It just takes so=
me
> > timing diagrams and head scratching. =A0And it's certainly not set up
> > for proper analysis especially in the Xilinx tools where I
> > experimented with the phase domain changes.
>
> It's not just FPGA tools. =A0Many of the high-end chip tools don't
> support this very well, and to do it you need a PhD in the tool.

The sad thing is it *shouldn't* be difficult.  For each stage of latch
traversed with an opposite clock edge, one more half cycle is added to
the overall timing spec for the path.  By analyzing up to each stage,
a logic delay short enough to change the input of a latch that's still
not transparent starts the timing path fresh from this intermediate
latch.

It's such a "pretty" cascade of logic delays that I have to research
what you mean by "domino logic" to make sure we're not talking about
the same thing.  It truly would be simple to analyze, no PhD required.

On Feb 14, 5:28=A0am, John_H <newsgr...@johnhandwork.com> wrote:
> On Feb 14, 12:17=A0am, Patrick Maupin <pmau...@gmail.com> wrote:
>
> > On Feb 13, 6:21=A0pm, John_H <newsgr...@johnhandwork.com> wrote:
>
> > > The description comes out a little muddy which is why it took me a fe=
w
> > > days to buy in to the whole concept. =A0It's sweet! =A0It just takes =
some
> > > timing diagrams and head scratching. =A0And it's certainly not set up
> > > for proper analysis especially in the Xilinx tools where I
> > > experimented with the phase domain changes.
>
> > It's not just FPGA tools. =A0Many of the high-end chip tools don't
> > support this very well, and to do it you need a PhD in the tool.
>
> The sad thing is it *shouldn't* be difficult. =A0For each stage of latch
> traversed with an opposite clock edge, one more half cycle is added to
> the overall timing spec for the path. =A0By analyzing up to each stage,
> a logic delay short enough to change the input of a latch that's still
> not transparent starts the timing path fresh from this intermediate
> latch.
>
> It's such a "pretty" cascade of logic delays that I have to research
> what you mean by "domino logic" to make sure we're not talking about
> the same thing. =A0It truly would be simple to analyze, no PhD required.

John_H,
Read this paper first, then make your conclusion.

"Timing Verification and Optimal Clocking of Synchronous Digital
Circuits", published by 3 professors in University of Michigan in
1990, known as SMO algorithm.

Weng

On Feb 12, 9:05=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I finally understand the reason when a flip-flops can be replaced by a
> latch.
> I saw the circuits before, but not realized what the basic reason was.
> With the above paper, I now know that the technology is not a new, it
> originated in 1980s.

Even earlier than that.

 Just look at the relative sales volumes of the venerable 74373 vs
74374.
 In all those cases, the latch is used to buy some extra setup time.

 Anywhere you find an ALE pin, you find this principle, and that goes
back a LONG way.

-jg

On Feb 16, 12:36=A0pm, -jg <jim.granvi...@gmail.com> wrote:
> On Feb 12, 9:05=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > Hi,
> > I finally understand the reason when a flip-flops can be replaced by a
> > latch.
> > I saw the circuits before, but not realized what the basic reason was.
> > With the above paper, I now know that the technology is not a new, it
> > originated in 1980s.
>
> Even earlier than that.
>
> =A0Just look at the relative sales volumes of the venerable 74373 vs
> 74374.
> =A0In all those cases, the latch is used to buy some extra setup time.
>
> =A0Anywhere you find an ALE pin, you find this principle, and that goes
> back a LONG way.
>
> -jg

jg,
I checked SN74LV374 TI's manual and couldn't find what you said: ALE
pin.

For time borrowing through a pipelined stages, Intel uses Domino Logic
which was not available until 2000.

Weng

Weng Tianxiang <wtxwtx@gmail.com> wrote:
> On Feb 16, 12:36?pm, -jg <jim.granvi...@gmail.com> wrote:

>> Even earlier than that.

>> ?Just look at the relative sales volumes of the venerable 74373 vs
>> | 74374. In all those cases, the latch is used to buy some extra 
>> | setup time.

>> ?Anywhere you find an ALE pin, you find this principle, and that 
>> | goes back a LONG way.

> I checked SN74LV374 TI's manual and couldn't find what you 
> said: ALE pin.

ALE is an output on, for example, many Intel processors.  Address
Latch Enable, such that the address can be latched while the pins
are used for other purposes.

The 8085 shares the data bus with part of the address bus, for example.
With a 74S373 the address is available for decoding long before ALE
goes low.  

-- glen

On Feb 16, 7:07=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Feb 16, 12:36=A0pm, -jg <jim.granvi...@gmail.com> wrote:
>
>
>
> > On Feb 12, 9:05=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > I finally understand the reason when a flip-flops can be replaced by =
a
> > > latch.
> > > I saw the circuits before, but not realized what the basic reason was=
.
> > > With the above paper, I now know that the technology is not a new, it
> > > originated in 1980s.
>
> > Even earlier than that.
>
> > =A0Just look at the relative sales volumes of the venerable 74373 vs
> > 74374.
> > =A0In all those cases, the latch is used to buy some extra setup time.
>
> > =A0Anywhere you find an ALE pin, you find this principle, and that goes
> > back a LONG way.
>
> > -jg
>
> jg,
> I checked SN74LV374 TI's manual and couldn't find what you said: ALE
> pin.
>
> For time borrowing through a pipelined stages, Intel uses Domino Logic
> which was not available until 2000.


The reason twofold.  One is that the pin was not called ALE on the
latch, it was called C or G or LE or something similar.  ALE is from
the Intel CPUs that require the latch to hold the address bits.  The
other reason is that you are looking at the wrong part.  The 373 part
is the latch and the 374 part is the register.  I am pretty sure the
only difference is the function of the clock input.

The latch is used with these processors for the exact reason you are
looking at latches.  It allows the output of the latch to output a
stable value from the input before the clock edge rather than after.
This was used to speed memory accesses.

Rick

rickman <gnuarm@gmail.com> wrote:
(snip)
 
> The latch is used with these processors for the exact reason you are
> looking at latches.  It allows the output of the latch to output a
> stable value from the input before the clock edge rather than after.
> This was used to speed memory accesses.

I still remember latches from when I first started learning about
TTL from Popular Electronics.  It was usual to connect a 7490 counter,
a 7475 latch and 7447 BCD to 7 segment decoder together.  You run
the counter, the display counts (maybe too fast to see), and then
latches at the appropriate time.  Sort of like a lap timer in
a race, which counts up, the latch holds the value while the
counter continues on.  After a short time the count continues
on for the next lap.  (I think they do this on olympics races.)

-- glen

On Feb 16, 5:38=A0pm, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:
> rickman <gnu...@gmail.com> wrote:
>
> (snip)
>
> > The latch is used with these processors for the exact reason you are
> > looking at latches. =A0It allows the output of the latch to output a
> > stable value from the input before the clock edge rather than after.
> > This was used to speed memory accesses.
>
> I still remember latches from when I first started learning about
> TTL from Popular Electronics. =A0It was usual to connect a 7490 counter,
> a 7475 latch and 7447 BCD to 7 segment decoder together. =A0You run
> the counter, the display counts (maybe too fast to see), and then
> latches at the appropriate time. =A0Sort of like a lap timer in
> a race, which counts up, the latch holds the value while the
> counter continues on. =A0After a short time the count continues
> on for the next lap. =A0(I think they do this on olympics races.)
>
> -- glen

glen,
I found a very good example on how to use a latch.

See Xilinx's patent: 5933369 "RAM with synchronous write port using
dynamic latches".

It describes the method Xilinx uses for its distributed RAM.

Weng