Modelsim PE vs. Aldec Active-HDL (PE)

On Mar 4, 8:07=A0am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote:
> =A0BOMK it has been expanded since then.
>

BOMK?

>I've finally decided to buy a better simulator
>(I've been making do with Modelsim XE so far).
>
>Any thoughts as to the relative merits of Modelsim PE and
>Active-HDL (PE) for FPGA simulation?
>
>Thanks
>
>Pete 
>
>

I have been using both Modelsim PE and Active HDL since last six years.
over the years , I have seen noticeable speed advantage of 2-3 times in
Active HDL-PE compared to Modelsim-PE. I also use lot of scripts to
simulate my designs and link files to AHDL without making local copies in
AHDL project.Well there is definite cost advantage with active HDL-PE.   

-Nick

	   
					
---------------------------------------		
Posted through http://www.FPGARelated.com

On Mar 3, 3:42=A0pm, d_s_klein <d_s_kl...@yahoo.com> wrote:
> On Mar 3, 5:02=A0am, "Pete Fraser" <pfra...@covad.net> wrote:
>
> > I've finally decided to buy a better simulator
> > (I've been making do with Modelsim XE so far).
>
> > Any thoughts as to the relative merits of Modelsim PE and
> > Active-HDL (PE) for FPGA simulation?
>
> > Thanks
>
> > Pete
>
> One complaint I have about Active-HDL is that it insists on making a
> copy of the sources and hiding them in a not so easy to find
> location. =A0It will then simulate these, and only these copies. =A0If yo=
u
> change a file while simulating, you have to remember to copy it out.
> If you change something between simulations, you have to re-import it.
>
> This "feature" makes the simulator mostly useful only *after* all the
> bugs are fixed. =A0(argh)

As Rick says, when you choose "Add New File," there is a check-box for
"Make Local Copy," which if de-selected seems to get grayed out so you
can never select it again. However when this is deselect the project
does not copy the file and instead references it from wherever it
lives.

I find Aldec's forced directory structure to be rather stupid, and
it's really difficult to put it reasonably into a source-code control
system. It wants to put all of the scripts and configuration files
into its src directory, which of course breaks the cardinal rule
"don't put synthesizable sources and configuration files in the same
directory!" and it's got too many configuration files. ModelSim has
one project file (the .mpf) which is plain text and easily edited by
hand.

I think it's whole notion of workspaces is pretty useless, too. It has
a potential to be useful, in that you can put multiple designs in it.
Consider, for instance, a design which has a top-level source and
three lower-level sources. Of course you want some kind of test bench
for each lower-level source, and it would seem that creating a
"Design" for each in the workspace would work. But it doesn't. One
reason is that each design has a library associated with it (and the
default name is NOT work, but rather the design name). You cannot have
a library that is shared among all of the designs in a workspace.
Also, you can't call the work library for each design "work" -- they
have to have different names. This all matters if you are lazy like me
and you use direct instantiation of lower-level entities:

   u_lower : entity work.lower port map (foo =3D> foo, bar =3D> bar);

I suppose the "right" thing to do in that case is to create a library
for each entity, analyze each into this library and instantiate from
it. This all assumes that your synthesis tool can support this.

Finally, I really like ModelSim's concept of "simulation
configurations." They're very easy -- you create a configuration, tell
it the top-level entity, set all of the generics and various other
things, and it's done. Click on the simulation configuration and off
you go. Sure, these things are nothing more than wrappers around the
vsim command but they're very handy. Active-HDL doesn't have this
feature, so the workaround is to create tcl scripts which call asim
with the proper command line.

So, yeah, Active-HDL is fine but if you are used to ModelSim's
features it can be confusing. I've spoken to Aldec's support folks
about the really fscking stupid forced directory structure, the
overabundance of configuration files and the lack of simulation
configurations. I don't know whether they will, or even can, change
some of this stuff without breaking existing projects, but as a paying
customer I guess I'm allowed to make suggestions.

-a

On Mar 4, 10:05=A0am, d_s_klein <d_s_kl...@yahoo.com> wrote:
> On Mar 4, 8:07=A0am, "cfelton" <cfelton@n_o_s_p_a_m.ieee.org> wrote:
>
> > =A0BOMK it has been expanded since then.
>
> BOMK?

"best of my knowledge."

-a

Andy Peters <google@latke.net> writes:

> ModelSim has one project file (the .mpf) which is plain text and
> easily edited by hand.

Various others have also mentioned project files and workspaces and
the like...

Am I the only one that makes *no* use of the various "project things"
(either in Modelsim or Aldec)?  I just have a makefile and use the GUI
to run the sim (from "their" command-line) and show me the waveforms.
I guess I don't like to be tied to a tool (as much as I can manage)
much as I don't like to be tied to a particular silicon vendor (as
much as I can manage :)

Am I missing something valuable, or is it just different?

Cheers,
Martin

-- 
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

> Am I the only one that makes *no* use of the various "project things"
> (either in Modelsim or Aldec)? =A0I just have a makefile and use the GUI
> to run the sim (from "their" command-line) and show me the waveforms.

I do the same so that makes at least two of us!  Scripts are best for
source control, staying sane and having weekends free...

Martin Thompson <martin.j.thompson@trw.com> writes:

> Am I the only one that makes *no* use of the various "project things"
> (either in Modelsim or Aldec)?  I just have a makefile and use the GUI

I almost always use my own set of command line tools to run the
simulation and eventually I use the waveform viewer for debugging.
I've been very happy with VCS in this regard.

I never use the bundled project or revision control stuff (I use
mostly git and/or svn).

Petter
-- 
A: Because it messes up the order in which people normally read text.
Q: Why is top-posting such a bad thing?
A: Top-posting.
Q: What is the most annoying thing on usenet and in e-mail?

On Mar 5, 5:34=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
> Andy Peters <goo...@latke.net> writes:
> > ModelSim has one project file (the .mpf) which is plain text and
> > easily edited by hand.
>
> Various others have also mentioned project files and workspaces and
> the like...
>
> Am I the only one that makes *no* use of the various "project things"
> (either in Modelsim or Aldec)? =A0I just have a makefile and use the GUI
> to run the sim (from "their" command-line) and show me the waveforms.
> I guess I don't like to be tied to a tool (as much as I can manage)
> much as I don't like to be tied to a particular silicon vendor (as
> much as I can manage :)
>
> Am I missing something valuable, or is it just different?

I doubt you are missing much of any real use.  I find the GUI will
save me a lot of typing when instantiating modules.  I use the
"generate test bench" feature to build a file with the meat and
potatoes in it and I copy that to the higher level module.

Otherwise if I was practiced in using make files with FPGA tools, I
would be likely be doing that too.

Rick

On Mar 5, 10:15=A0am, rickman <gnu...@gmail.com> wrote:
> On Mar 5, 5:34=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
> > Andy Peters <goo...@latke.net> writes:
> > > ModelSim has one project file (the .mpf) which is plain text and
> > > easily edited by hand.
>
> > Various others have also mentioned project files and workspaces and
> > the like...
>
> > Am I the only one that makes *no* use of the various "project things"
> > (either in Modelsim or Aldec)? =A0I just have a makefile and use the GU=
I
> > to run the sim (from "their" command-line) and show me the waveforms.
> > I guess I don't like to be tied to a tool (as much as I can manage)
> > much as I don't like to be tied to a particular silicon vendor (as
> > much as I can manage :)
>
> > Am I missing something valuable, or is it just different?
>
> I doubt you are missing much of any real use. =A0I find the GUI will
> save me a lot of typing when instantiating modules. =A0I use the
> "generate test bench" feature to build a file with the meat and
> potatoes in it and I copy that to the higher level module.
>
> Otherwise if I was practiced in using make files with FPGA tools, I
> would be likely be doing that too.

I don't use any of the Aldec tools that automatically generate test
benches or creating instances and all of that. Yes, I'm an emacs vhdl-
mode user and emacs does a fantabulous job of all of that.

Right now I'm working through the "best" way to set up projects within
the GUI, with an eye towards taking this and generating a Makefile or
a script or something.

It turns out that it is reasonable to create one workspace for an FPGA
project and within this workspace create a "design" for the
subentities and the top level. If you let it use the design name as
the working library for the design, then as long as you "use" the
library in a higher-level source, that source can see those other
libraries.

Now I'm thinking that the usual method of doing:

    u_foo : entity work.foo port map (bar =3D> bar, bletch =3D> bletch);

might be better as:

    u_foo : entity foo.foo port map (bar =3D> bar, bletch =3D> bletch);

The other option is to create a package with a component definition
for foo, and analyze that package into the foo library, so the
instantiation can be:

    u_foo : foo port map (bar =3D> bar, bletch =3D> bletch);

I really don't know which is "better."

-a

On Mar 5, 5:34=A0am, Martin Thompson <martin.j.thomp...@trw.com> wrote:
>
> Am I the only one that makes *no* use of the various "project things"
> (either in Modelsim or Aldec)? =A0I just have a makefile and use the GUI
> to run the sim (from "their" command-line) and show me the waveforms.
> I guess I don't like to be tied to a tool (as much as I can manage)
> much as I don't like to be tied to a particular silicon vendor (as
> much as I can manage :)
>

But you're also running *their* commands to compile, run and view so
you're not really any more independent.  Maintaining make files can be
a chore also, unless you use something to help you manage it...but
then you're now dependent on that tool as well.

> Am I missing something valuable, or is it just different?
>
Probably depends on which scenario is more likely to occur
1. Change sim tools
2. Add new developers (temporary, or because you move on to something
else in the company)

If #1 is prevalent, then maybe using other tools to help you manage
'make' is better.  If #2 is more prevalent, then using the tool's
project system is probably better in easing the transition.  If
neither is particularly likely...well...then it probably doesn't much
matter since one can probably be just as productive with various
approaches.

Kevin Jennings