Hello to all !
I've problem with finite state machine. Because I have not much place in my
FPGA and I need to create few more FSM i found that FSM logic can be packed
in to BRAM. I created simple FSM in VHDL and it shows in raport that it
uses Bram but there is a warning :
WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please
check that the RAM contents is read synchronously.
I tried to make the simplest FSM but it dont change anything...
Can someone show me an example of code in VHDL of simple state machine that
can be packed in to BRAM with any warnings, errors. I just worry that my
design won't work. I have ISE 11.1 and Spartan 3a...
Thanks for any response...
XST log :
Reading design: binary.prj
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "C:/FPGA PRAM/Debug/MultiCore/Example.vhd" in Library
work.
Architecture behv of Entity binary is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <binary> in library <work> (architecture
<behv>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <binary> in library <work> (Architecture <behv>).
Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal
<CS>.
Set property "ENUM_ENCODING = 001 010 011 100 101 110 111" for signal
<NS>.
Entity <binary> analyzed. Unit <binary> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <binary>.
Related source file is "C:/FPGA PRAM/Debug/MultiCore/Example.vhd".
Found finite state machine <FSM_0> for signal <CS>.
-----------------------------------------------------------------------
| States | 7
|
| Transitions | 16
|
| Inputs | 6
|
| Outputs | 3
|
| Clock | CLOCK (rising_edge)
|
| Power Up State | s1
|
| Encoding | compact
|
| Implementation | BRAM
|
-----------------------------------------------------------------------
Summary:
inferred 1 Finite State Machine(s).
Unit <binary> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
Implementing FSM <FSM_0> on signal <CS> on BRAM.
Synthesizing (advanced) Unit <CS>.
WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please
check that the RAM contents is read synchronously.
-----------------------------------------------------------------------
| ram_type | Block |
|
-----------------------------------------------------------------------
| Port A
|
| aspect ratio | 512-word x 6-bit |
|
| mode | write-first |
|
| clkA | connected to signal <Clk_FSM> | rise
|
| weA | connected to internal node | high
|
| addrA | connected to signal <In0> |
|
| diA | connected to internal node |
|
| doA | connected to signal <Out2> |
|
-----------------------------------------------------------------------
| optimization | area |
|
-----------------------------------------------------------------------
Unit <CS> synthesized (advanced).
=========================================================================
Advanced HDL Synthesis Report
Macro Statistics
# FSMs : 1
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <binary> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block binary, actual ratio is
0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Clock Information:
------------------
-----------------------------------+------------------------+-------+
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
CLOCK | BUFGP | 1 |
-----------------------------------+------------------------+-------+
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: 2.625ns (Maximum Frequency: 380.952MHz)
Minimum input arrival time before clock: 1.342ns
Maximum output required time after clock: 6.860ns
Maximum combinational path delay: No path found
=========================================================================
Process "Synthesis" completed successfully
---------------------------------------
Posted through http://www.FPGARelated.com
FSM in BlockRAM
Started by ●March 5, 2010
Reply by ●March 5, 20102010-03-05
On 3/5/2010 11:39 AM, de4 wrote:> > Can someone show me an example of code in VHDL of simple state machine that > can be packed in to BRAM with any warnings, errors. I just worry that my > design won't work. I have ISE 11.1 and Spartan 3a... >XAPP291
Reply by ●March 5, 20102010-03-05
On Mar 5, 2:41=A0pm, Symon <symon_bre...@hotmail.com> wrote:> On 3/5/2010 11:39 AM, de4 wrote: > > > > > Can someone show me an example of code in VHDL of simple state machine =that> > can be packed in to BRAM with any warnings, errors. I just worry that m=y> > design won't work. I have ISE 11.1 and Spartan 3a... > > XAPP291xapp291 does NOT show how from SM VHDL code a implementation using BRAM is generated by the tools Antti
Reply by ●March 5, 20102010-03-05
On 3/5/2010 4:08 PM, Antti wrote:> On Mar 5, 2:41 pm, Symon<symon_bre...@hotmail.com> wrote: >> On 3/5/2010 11:39 AM, de4 wrote: >> >> >> >>> Can someone show me an example of code in VHDL of simple state machine that >>> can be packed in to BRAM with any warnings, errors. I just worry that my >>> design won't work. I have ISE 11.1 and Spartan 3a... >> >> XAPP291 > > xapp291 does NOT show how from SM VHDL code a implementation using > BRAM is generated by the tools > > AnttiBut it _IS_ an example of 'code in VHDL of [a] simple state machine that can be packed in to BRAM'. Syms.
Reply by ●March 5, 20102010-03-05
On Mar 5, 4:39=A0am, "de4" <de4@n_o_s_p_a_m.poczta.onet.pl> wrote:> Hello to all ! > > I've problem with finite state machine. Because I have not much place in =my> FPGA and I need to create few more FSM i found that FSM logic can be pack=ed> in to BRAM. I created simple FSM in VHDL and it shows =A0in raport that i=t> uses Bram but there is a warning : > > WARNING:Xst - Cannot use block RAM resources for signal <FSMROM>. Please > check that the RAM contents is read synchronously. > > I tried to make the simplest FSM but it dont change anything...Are you using the two-process state machine construct? If so, DON'T. -a
Reply by ●March 5, 20102010-03-05
On Mar 5, 8:08=A0am, Antti <antti.luk...@googlemail.com> wrote:> On Mar 5, 2:41=A0pm, Symon <symon_bre...@hotmail.com> wrote: > > > On 3/5/2010 11:39 AM, de4 wrote: > > > > Can someone show me an example of code in VHDL of simple state machin=e that> > > can be packed in to BRAM with any warnings, errors. I just worry that=my> > > design won't work. I have ISE 11.1 and Spartan 3a... > > > XAPP291 > > xapp291 does NOT show how from SM VHDL code a implementation using > BRAM is generated by the tools > > AnttiThis is a very simple design, easily implemented in BRAM (if speed permits) You have 7 states, therefore you need 3 (encoded) outputs You have 6 incoming condition or jump codes. You use the BRAM as a synchronous look-up table, using as address the combination of any jump code with any state code. That means you need 9 inputs, and the BRAM is thus 512 x 3. ( "512 x 6" in your posting is nonsense) In hardware you must feed the three output bits back to the address inputs. You can use any additional otherwise unused outputs as decoded state descriptors, but that does not change the basic design. I suppose you know that the addressing information is automatically registered before it addresses the BRAM (which is really a BROM with fixed data content) Do not use any additional output pipelining, optionally available in some devices. Unfortunately I cannot give you any VHDL code, but the basic understanding should help you. I have described and promoted this type of design for many years. Peter Alfke, formerly Xilinx Applications (some of you may remember me)
Reply by ●March 5, 20102010-03-05
Peter Alfke <alfke@sbcglobal.net> wrote: (snip)> Peter Alfke, formerly Xilinx Applications (some of you may remember me)and also notice that you don't post as often as before. I was not so long ago thinking of asking: There is picoblaze (8 bit), and microblaze (32 bit), but no nanoblaze (16 bit) or milliblaze (64 bit). It might even be interesting to have a femtoblaze (4 bit) processor. Maybe not so far off topic, as such processors are, at some level, complicated state machines. -- glen
Reply by ●March 5, 20102010-03-05
On Mar 5, 11:10=A0am, glen herrmannsfeldt <g...@ugcs.caltech.edu> wrote:> Peter Alfke <al...@sbcglobal.net> wrote: > > (snip) > > > Peter Alfke, formerly Xilinx Applications (some of you may remember me) > > and also notice that you don't post as often as before. > > I was not so long ago thinking of asking: > > =A0 =A0There is picoblaze (8 bit), and microblaze (32 bit), but no > =A0 =A0nanoblaze (16 bit) or milliblaze (64 bit). =A0It might even > =A0 =A0be interesting to have a femtoblaze (4 bit) processor. > > Maybe not so far off topic, as such processors are, at some level, > complicated state machines. > > -- glenBlazes... "Picoblaze" was started by Ken Chapman (still at Xilinx UK) as a highly optimized design, an app note that works well with 4-input LUTs and BRAMs. Xilinx has unfortunately always treated it as an illiigitimate child. (NIH) It lives due to its efficiency, and due to Ken's competence, enthusiasm, and perseverance. "Microblaze" was started by Goran Bilski (originally in Sweden, and now, after some years in Calif., back again in Sweden.) It has always been treated as a legitimate Xilinx baby, and Goran has continuously improved it, and more designers are involved. It grew from 16 bits to 32 bits. Still a highly optimized design. I have no idea about plans for 64 bits. I visit the Xilinx cafeteria once every couple of months to chat with old friends. I did repeatedly offer my services as a consultant, even without pay, but there are no takers. Peter A.
Reply by ●March 6, 20102010-03-06
Peter Alfke wrote:> I did repeatedly offer my services as a consultant, even without pay, > but there are no takers.Is it because of "budget restrictions" or because... you're outside the company's loop now ? are you an "outcast" already ?> Peter A.yg -- http://ygdes.com / http://yasep.org
Reply by ●March 6, 20102010-03-06
On Mar 6, 1:59=A0am, whygee <y...@yg.yg> wrote:> Peter Alfke wrote: > > I did repeatedly offer my services as a consultant, even without pay, > > but there are no takers. > > Is it because of "budget restrictions" or because... > you're outside the company's loop now ? > are you an "outcast" already ? > > > Peter A. > > yg > > --http://ygdes.com/http://yasep.orgAll of it... But don't feel sorry for me, I am fine. Feel sorry for a company that is too hung up to take advantage of an available resource. Peter A
