Why doesn't this situation generate a latch?

Hi,
I have a question about when to generate a latch.

In Example_1 and Exmaple_2, I don't think it will generate a latch. I
don't know why.

Example_1: process(RESET, CLK)
Begin
	If RESET =3D =911=92 then
		StateA <=3D S0;
	Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
		If SINI =3D =911=92 then
			StateA <=3D S0;
		Elsif E2 =3D =911=92 then
			null;			-- missing a signal assignment statement
						-- I suppose it will not generate a latch, why?
		Elsif StateA =3D S1 then
			StateA <=3D S3;
		Else
			StateA <=3D StateA_NS;
		End if;
	End if;
End process;

Example_2: process(=85)
Begin
	Case StateA is
		...;		-- no signal assignement statements are missing
	End case;
End process;

Weng

On Mar 8, 5:46=A0pm, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I have a question about when to generate a latch.
>
> In Example_1 and Exmaple_2, I don't think it will generate a latch. I
> don't know why.
>
> Example_1: process(RESET, CLK)
> Begin
> =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why?
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> =A0 =A0 =A0 =A0 End if;
> End process;
>
> Example_2: process(=85)
> Begin
> =A0 =A0 =A0 =A0 Case StateA is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal =
assignement statements are missing
> =A0 =A0 =A0 =A0 End case;
> End process;
>
> Weng

It doesn't generate a latch because you have fully defined a positive
edge triggered register with an asynchronous reset.

The result of the "Elsif E2 =3D '1' " comparison is that StateA remains
the same as it was in the previous clk'event and this takes precedence
over the next Elsif and Else statements.

Ed McGettigan
--
Xilinx Inc.

On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote:
> Hi,
> I have a question about when to generate a latch.
>
> In Example_1 and Exmaple_2, I don't think it will generate a latch. I
> don't know why.
>
> Example_1: process(RESET, CLK)
> Begin
> =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why?
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS;
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> =A0 =A0 =A0 =A0 End if;
> End process;
>
> Example_2: process(=85)
> Begin
> =A0 =A0 =A0 =A0 Case StateA is
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal =
assignement statements are missing
> =A0 =A0 =A0 =A0 End case;
> End process;
>
> Weng

In my mind, it generated a register with enable and async reset.
Latches are only created when you dont have a clock in a process and
you forget to assign something between process iterations.

On Mar 9, 12:32=A0am, Tricky <trickyh...@gmail.com> wrote:
> On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > Hi,
> > I have a question about when to generate a latch.
>
> > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
> > don't know why.
>
> > Example_1: process(RESET, CLK)
> > Begin
> > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why?
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS;
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> > =A0 =A0 =A0 =A0 End if;
> > End process;
>
> > Example_2: process(=85)
> > Begin
> > =A0 =A0 =A0 =A0 Case StateA is
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signa=
l assignement statements are missing
> > =A0 =A0 =A0 =A0 End case;
> > End process;
>
> > Weng
>
> In my mind, it generated a register with enable and async reset.
> Latches are only created when you dont have a clock in a process and
> you forget to assign something between process iterations.

Example_1: process(RESET, CLK)
Begin
   If RESET =3D =911=92 then
      StateA <=3D S0;
   Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
      If SINI =3D =911=92 then
         StateA <=3D S0;
      Elsif E2 =3D =911=92 then
         null;    -- missing a signal assignment statement
                  -- I suppose it will not generate a latch, why?
      Elsif StateA =3D S1 then
         StateA <=3D S3;
      Elsif C1 /=3D '1' then
         StateA <=3D StateA_NS;
   -- else         -- missing a signal assignment statement
   --    null;     -- I suppose it will not generate a latch, why?
      End if;
   End if;
End process;

Example_2: process(=85)
Begin
   Case StateA is
      ...;            -- no signal assignement statements are missing
   End case;
End process;

Weng

On Mar 9, 7:24=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
> On Mar 9, 12:32=A0am, Tricky <trickyh...@gmail.com> wrote:
>
>
>
>
>
> > On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > Hi,
> > > I have a question about when to generate a latch.
>
> > > In Example_1 and Exmaple_2, I don't think it will generate a latch. I
> > > don't know why.
>
> > > Example_1: process(RESET, CLK)
> > > Begin
> > > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 the=
n
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why?
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_NS=
;
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> > > =A0 =A0 =A0 =A0 End if;
> > > End process;
>
> > > Example_2: process(=85)
> > > Begin
> > > =A0 =A0 =A0 =A0 Case StateA is
> > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no sig=
nal assignement statements are missing
> > > =A0 =A0 =A0 =A0 End case;
> > > End process;
>
> > > Weng
>
> > In my mind, it generated a register with enable and async reset.
> > Latches are only created when you dont have a clock in a process and
> > you forget to assign something between process iterations.
>
> Example_1: process(RESET, CLK)
> Begin
> =A0 =A0If RESET =3D =911=92 then
> =A0 =A0 =A0 StateA <=3D S0;
> =A0 =A0Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> =A0 =A0 =A0 If SINI =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0StateA <=3D S0;
> =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> =A0 =A0 =A0 =A0 =A0null; =A0 =A0-- missing a signal assignment statement
> =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a l=
atch, why?
> =A0 =A0 =A0 Elsif StateA =3D S1 then
> =A0 =A0 =A0 =A0 =A0StateA <=3D S3;
> =A0 =A0 =A0 Elsif C1 /=3D '1' then
> =A0 =A0 =A0 =A0 =A0StateA <=3D StateA_NS;
> =A0 =A0-- else =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> =A0 =A0-- =A0 =A0null; =A0 =A0 -- I suppose it will not generate a latch,=
 why?
> =A0 =A0 =A0 End if;
> =A0 =A0End if;
> End process;
>
> Example_2: process(=85)
> Begin
> =A0 =A0Case StateA is
> =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal assignement statemen=
ts are missing
> =A0 =A0End case;
> End process;
>
> Weng- Hide quoted text -
>
> - Show quoted text -

It isn't clear what you are looking for or trying learn with this code
snippets.  In both case these are the classical register coding
styles.

1) The process has two signals, RESET and CLK, in the sensitivity list
2) There is only one signal, StateA, assignment
3) The RESET is coded as an active high level asynchronous reset
function
     Note: S0 should be a fixed static value or this will cause
problems
4) The CLK is coded as a rising edge clock and generates the register
element.
     Note: Everything within this ELSIF statement is evaluated only on
the rising edge

I would strongly encourage you to change the RESET function from
asynchronous to synchronous.

Ed McGettigan
--
Xilinx Inc.

On Mar 9, 10:15=A0am, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> On Mar 9, 7:24=A0am, Weng Tianxiang <wtx...@gmail.com> wrote:
>
>
>
>
>
> > On Mar 9, 12:32=A0am, Tricky <trickyh...@gmail.com> wrote:
>
> > > On 9 Mar, 01:46, Weng Tianxiang <wtx...@gmail.com> wrote:
>
> > > > Hi,
> > > > I have a question about when to generate a latch.
>
> > > > In Example_1 and Exmaple_2, I don't think it will generate a latch.=
 I
> > > > don't know why.
>
> > > > Example_1: process(RESET, CLK)
> > > > Begin
> > > > =A0 =A0 =A0 =A0 If RESET =3D =911=92 then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > > > =A0 =A0 =A0 =A0 Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 t=
hen
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 If SINI =3D =911=92 then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S0;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 null; =A0 =A0 =A0 =
=A0 =A0 =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0=
 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a latch, why=
?
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Elsif StateA =3D S1 then
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D S3;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 Else
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 StateA <=3D StateA_=
NS;
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 End if;
> > > > =A0 =A0 =A0 =A0 End if;
> > > > End process;
>
> > > > Example_2: process(=85)
> > > > Begin
> > > > =A0 =A0 =A0 =A0 Case StateA is
> > > > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no s=
ignal assignement statements are missing
> > > > =A0 =A0 =A0 =A0 End case;
> > > > End process;
>
> > > > Weng
>
> > > In my mind, it generated a register with enable and async reset.
> > > Latches are only created when you dont have a clock in a process and
> > > you forget to assign something between process iterations.
>
> > Example_1: process(RESET, CLK)
> > Begin
> > =A0 =A0If RESET =3D =911=92 then
> > =A0 =A0 =A0 StateA <=3D S0;
> > =A0 =A0Elsif CLK=92event =3D =911=92 and CLK =3D =911=92 then
> > =A0 =A0 =A0 If SINI =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0StateA <=3D S0;
> > =A0 =A0 =A0 Elsif E2 =3D =911=92 then
> > =A0 =A0 =A0 =A0 =A0null; =A0 =A0-- missing a signal assignment statemen=
t
> > =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 =A0 -- I suppose it will not generate a=
 latch, why?
> > =A0 =A0 =A0 Elsif StateA =3D S1 then
> > =A0 =A0 =A0 =A0 =A0StateA <=3D S3;
> > =A0 =A0 =A0 Elsif C1 /=3D '1' then
> > =A0 =A0 =A0 =A0 =A0StateA <=3D StateA_NS;
> > =A0 =A0-- else =A0 =A0 =A0 =A0 -- missing a signal assignment statement
> > =A0 =A0-- =A0 =A0null; =A0 =A0 -- I suppose it will not generate a latc=
h, why?
> > =A0 =A0 =A0 End if;
> > =A0 =A0End if;
> > End process;
>
> > Example_2: process(=85)
> > Begin
> > =A0 =A0Case StateA is
> > =A0 =A0 =A0 ...; =A0 =A0 =A0 =A0 =A0 =A0-- no signal assignement statem=
ents are missing
> > =A0 =A0End case;
> > End process;
>
> > Weng- Hide quoted text -
>
> > - Show quoted text -
>
> It isn't clear what you are looking for or trying learn with this code
> snippets. =A0In both case these are the classical register coding
> styles.
>
> 1) The process has two signals, RESET and CLK, in the sensitivity list
> 2) There is only one signal, StateA, assignment
> 3) The RESET is coded as an active high level asynchronous reset
> function
> =A0 =A0 =A0Note: S0 should be a fixed static value or this will cause
> problems
> 4) The CLK is coded as a rising edge clock and generates the register
> element.
> =A0 =A0 =A0Note: Everything within this ELSIF statement is evaluated only=
 on
> the rising edge
>
> I would strongly encourage you to change the RESET function from
> asynchronous to synchronous.
>
> Ed McGettigan
> --
> Xilinx Inc.

Ed,
Thank you.

Weng

Weng,

Let's look at what behavior generates a latch: The need for the
circuit to remember a previous assignment from a previous execution of
the process, when no other storage media is implied (i.e. in a
combinatorial process). In a clocked process, the register does the
remembering, since the process will have to remember the previous
assignment when it executes on the falling edge too). A clock enable
is added when the process must remember over more than one clock
cycle.

Looking at it another way, conceptually, a latch is nothing than a mux
with feedback around whatever the input logic was (combinatorial). A
register with clock enable is conceptually just a mux with feedback
too, but the feedback is from the output of the register back to its
input. So, in a combinatorial process with a missed assignment, you
get a latch, whereas in a clocked process, it gets implemented with a
clock enable on the register, and no latch is needed.

Some synthesis tools may be getting smart enough to optimize an
inferred latch from a combinatorial process into a clock enable on the
corresponding register implied by the clocked process. But if there
are any other combinatorial processes that use that latched output of
the first combinatorial process, then the latch cannot be replaced by
a clock enable on a register.

Andy

On Mar 9, 12:15=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
> I would strongly encourage you to change the RESET function from
> asynchronous to synchronous.

On what basis do you make this recommendation, and what does this have
to do with latches?

Andy

On Mar 10, 10:06=A0am, Andy <jonesa...@comcast.net> wrote:
> On Mar 9, 12:15=A0pm, Ed McGettigan <ed.mcgetti...@xilinx.com> wrote:
>
> > I would strongly encourage you to change the RESET function from
> > asynchronous to synchronous.
>
> On what basis do you make this recommendation, and what does this have
> to do with latches?
>
> Andy

Please allow me to chime in with a basic tutorial:
Latches and flip/flops=3Dregisters have common features and also a big
difference:
They both are storage elements, both have a Data input (D) and a data
output ( Q), and both have a control input called Enable or Clock.
(Let me ignore the contentious issue of asynchronous or synchronous
Reset/clear or Preset)

The big difference:
A latch is transparent,( i.e. Q follows D, and thus there is no
storage), whenever the Enable input is active. But Data is stored when
Enable is inactive.
A flip-flop is NEVER transparent. (D can never affect Q directly). Q
assumes the state that D had right before the rising edge of the
clock.

How is this done?
Inside the flip-flop, there are two cascaded latches (called Master
and Slave).
The Master latch is transparent and its internal output follows the D
input as long as the Clock is low.
The Slave latch is transparent and its external output Q follows the
slave's internal output whenever the Clock is High, but during this
time the Master is non-transparent =3D locked up.
So the two cascaded latches have the opposite enable polarity.
Thus the flip-flop's Q output can only change on (i.e. right after)
the rising clock edge.

I do not want to belabor the advantages of either design, just to
avoid confusion.
The flip-flop or register is the prevalent design. It wins the Oscar
in most (but not all) cases..., but RAM cells always use the simpler
latch structure.

Peter Alfke, (teacher at heart)

In comp.arch.fpga Peter Alfke <alfke@sbcglobal.net> wrote:
(snip) 

> I do not want to belabor the advantages of either design, 
> just to avoid confusion.

> The flip-flop or register is the prevalent design. It wins the Oscar
> in most (but not all) cases..., but RAM cells always use the simpler
> latch structure.

To be more specific, SRAM.  Now, are there more SRAM cells around
than registers bits in processors?  If you count SRAM in processor
cache memory it might be that there are more.

For the first digital logic class I had, all the classroom 
demonstrations were done with paired RS flip-flops and
a two phase clock.  It does make it easier to understand in
a classroom setting.  Also, many past processors did use a
two (or more) phase clock.  (I remember stories about the
four phase clock for the TMS9900.)  

It would be interesting to have an FPGA with transparent latches
after each LUT instead of the current edge triggered FFs.

-- glen