I think I fried my I/O bank... (virtex-E question)

Quick question... I've been using a Virtex-E fpga on a development
board that provides jumpers to connect or disconnect Vcco for each I/O
bank.  Some of my inputs are LVDS, and one of my signal sources has
LVDS output that swings up as high as ~2.4V at the highest.  On one of
my last test runs I accidentally left the Vcco jumper uninstalled for
the IO bank that this device was connected to, meaning that Vcco for
that bank was left floating.  To make a long story short, much current
was drawn, and now (probing the FPGA pins directly) Vcco for that I/O
bank appears to be shorted to ground inside the chip package(~1.5 ohms
from Vcco pin to Gnd pin).

To anyone out there who's familiar with Xilinx hardware, would the
mistake I made above (no Vcco for a ~2.4V input LVDS signal) have
caused the IO bank to become damaged?  I'd just like some confirmation
that this is the cause, before I power up the FPGA board and fry
another IO bank...

Not,

Seems extremely unlikely.  It is true that without Vcco connected to 
anything, the ESD protection as well as the other protection circuits 
for large positive voltages is not well protected.

Is this attached to a long cable?  If so, you may blow out the IOBs even 
with the Vcco connected (inductive kickback can cause very large voltages).

For long cable applciations, clamp diodes are almost required.

Austin

NotTooSmart wrote:
> Quick question... I've been using a Virtex-E fpga on a development
> board that provides jumpers to connect or disconnect Vcco for each I/O
> bank.  Some of my inputs are LVDS, and one of my signal sources has
> LVDS output that swings up as high as ~2.4V at the highest.  On one of
> my last test runs I accidentally left the Vcco jumper uninstalled for
> the IO bank that this device was connected to, meaning that Vcco for
> that bank was left floating.  To make a long story short, much current
> was drawn, and now (probing the FPGA pins directly) Vcco for that I/O
> bank appears to be shorted to ground inside the chip package(~1.5 ohms
> from Vcco pin to Gnd pin).
> 
> To anyone out there who's familiar with Xilinx hardware, would the
> mistake I made above (no Vcco for a ~2.4V input LVDS signal) have
> caused the IO bank to become damaged?  I'd just like some confirmation
> that this is the cause, before I power up the FPGA board and fry
> another IO bank...