how to use the design results of the vhdl code for a program in C code

hello,
i need help.
i work over an algo in C langage that verifies a design described in
VHDL
for it, i want take all informations from my vhdl code for use them in
my programme in C and i don't know how.

On Mon, 15 Mar 2010 02:51:22 -0700 (PDT), lolita grenoble
<lolita.grenoble@gmail.com> wrote:

>hello,
>i need help.
>i work over an algo in C langage that verifies a design described in
>VHDL
>for it, i want take all informations from my vhdl code for use them in
>my programme in C and i don't know how.

One way is to write a file in your VHDL code (running it in the simulator)
then read that file in your C code.

- Brian

On Mon, 15 Mar 2010 12:07:24 +0000
Brian Drummond <brian_drummond@btconnect.com> wrote:

> On Mon, 15 Mar 2010 02:51:22 -0700 (PDT), lolita grenoble
> <lolita.grenoble@gmail.com> wrote:
> 
> >hello,
> >i need help.
> >i work over an algo in C langage that verifies a design described in
> >VHDL
> >for it, i want take all informations from my vhdl code for use them
> >in my programme in C and i don't know how.
> 
> One way is to write a file in your VHDL code (running it in the
> simulator) then read that file in your C code.
> 
> - Brian

Specifically, your search term is STD.TEXTIO

-- 
Rob Gaddi, Highland Technology
Email address is currently out of order

On Mon, 15 Mar 2010 09:27:02 -0700, Rob Gaddi <rgaddi@technologyhighland.com>
wrote:

>On Mon, 15 Mar 2010 12:07:24 +0000
>Brian Drummond <brian_drummond@btconnect.com> wrote:
>
>> On Mon, 15 Mar 2010 02:51:22 -0700 (PDT), lolita grenoble
>> <lolita.grenoble@gmail.com> wrote:
>> 
>> >hello,
>> >i need help.
>> >i work over an algo in C langage that verifies a design described in
>> >VHDL
>> >for it, i want take all informations from my vhdl code for use them
>> >in my programme in C and i don't know how.
>> 
>> One way is to write a file in your VHDL code (running it in the
>> simulator) then read that file in your C code.
>> 
>> - Brian
>
>Specifically, your search term is STD.TEXTIO

Indeed. You can write binary files (e.g. .bmp images) from VHDL but the details
are not defined so the result is not necessarily portable. Modelsim is
straightforward but Xilinx ISE Simulator is not.

- Brian