I'm having a terrible time finding a solution to a library problem. I am implementing some IWLS benchmarks on a Spartan3e, and I need some standard cells such as: AOI21X1 AND3X1 AND2X1 NAND2X1 etc. Does anyone have a suggestion? Am I overlooking something simple? Thanks in advance. -- Jason Thibodeau
Standard cell library help
Started by ●March 22, 2010
Reply by ●March 22, 20102010-03-22
On Mar 22, 5:42=A0pm, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote:> I'm having a terrible time finding a solution to a library problem. > > I am implementing some IWLS benchmarks on a Spartan3e, and I need some > standard cells such as: > > AOI21X1 > AND3X1 > AND2X1 > NAND2X1 > > etc. > > Does anyone have a suggestion? Am I overlooking something simple? > > Thanks in advance. > -- > Jason ThibodeauThe standard cell library should document the function of each these cells. Likely guesses are. AOI21X1 - 2-Input AND-OR with Inversion on inputs? AND3X1 - 3-Input AND AND2X1 - 2-Input AND NAND2X1 - 2-Input NAND etc... =3D etc... :-) Ed McGettigan -- Xilinx Inc.
Reply by ●March 23, 20102010-03-23
On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan <ed.mcgettigan@xilinx.com> wrote:>On Mar 22, 5:42�pm, Jason Thibodeau <jason.p.thibod...@gmail.com> >wrote: >> I'm having a terrible time finding a solution to a library problem. >> >> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >> standard cells such as: >> >> AOI21X1 >> AND3X1 >> AND2X1 >> NAND2X1 >> >> etc. >> >> Does anyone have a suggestion? Am I overlooking something simple? >> >> Thanks in advance. >> -- >> Jason Thibodeau > >The standard cell library should document the function of each these >cells. Likely guesses are. > >AOI21X1 - 2-Input AND-OR with Inversion on inputs? >AND3X1 - 3-Input AND >AND2X1 - 2-Input AND >NAND2X1 - 2-Input NAND > >etc... = etc... :-) > >Ed McGettiganIf we had more info, we can make better guesses. The ports are extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which is OR-inverted with the third ie y = !((a0&a1) | b0). One more thing which is again very helpful is to get the simulation model of the standard cell library and use it without any timing as the behavioral model. Synthesis tools do a pretty decent job of doing the mapping. -- Muzaffer Kal DSPIA INC. ASIC/FPGA Design Services http://www.dspia.com
Reply by ●March 23, 20102010-03-23
I'm sorry, Kal and Ed, I should have been more specific. I know what the gates are, but they are not defined in the code anywhere. I am figuring I need to include a library where they will be defined, but I don't know which I should be using, or if any are even available in the Xilinx flow. I import the (verilog) benchmark, instantiate it in my VHDL toplevel, and when it is synthesized, I have 614 errors since the gates are not defined. I was hoping it would be something as simple as including a library. On 03/23/2010 12:47 AM, Muzaffer Kal wrote:> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > <ed.mcgettigan@xilinx.com> wrote: > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >> wrote: >>> I'm having a terrible time finding a solution to a library problem. >>> >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>> standard cells such as: >>> >>> AOI21X1 >>> AND3X1 >>> AND2X1 >>> NAND2X1 >>> >>> etc. >>> >>> Does anyone have a suggestion? Am I overlooking something simple? >>> >>> Thanks in advance. >>> -- >>> Jason Thibodeau >> >> The standard cell library should document the function of each these >> cells. Likely guesses are. >> >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >> AND3X1 - 3-Input AND >> AND2X1 - 2-Input AND >> NAND2X1 - 2-Input NAND >> >> etc... = etc... :-) >> >> Ed McGettigan > > If we had more info, we can make better guesses. The ports are > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > is OR-inverted with the third ie y = !((a0&a1) | b0). > One more thing which is again very helpful is to get the simulation > model of the standard cell library and use it without any timing as > the behavioral model. Synthesis tools do a pretty decent job of doing > the mapping.-- Jason Thibodeau www.jayt.org
Reply by ●March 23, 20102010-03-23
On Mar 23, 8:17=A0am, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote:> I'm sorry, Kal and Ed, I should have been more specific. > > I know what the gates are, but they are not defined in the code > anywhere. I am figuring I need to include a library where they will be > defined, but I don't know which I should be using, or if any are even > available in the Xilinx flow. > > I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > and when it is synthesized, I have 614 errors since the gates are not > defined. > > I was hoping it would be something as simple as including a library. > > On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > > On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > <ed.mcgetti...@xilinx.com> =A0wrote: > > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > >> wrote: > >>> I'm having a terrible time finding a solution to a library problem. > > >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need som=e> >>> standard cells such as: > > >>> AOI21X1 > >>> AND3X1 > >>> AND2X1 > >>> NAND2X1 > > >>> etc. > > >>> Does anyone have a suggestion? Am I overlooking something simple? > > >>> Thanks in advance. > >>> -- > >>> Jason Thibodeau > > >> The standard cell library should document the function of each these > >> cells. =A0Likely guesses are. > > >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > >> AND3X1 - 3-Input AND > >> AND2X1 - 2-Input AND > >> NAND2X1 - 2-Input NAND > > >> etc... =3D etc... :-) > > >> Ed McGettigan > > > If we had more info, we can make better guesses. The ports are > > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > > is OR-inverted =A0with the third ie y =3D !((a0&a1) | b0). > > One more thing which is again very helpful is to get the simulation > > model of the standard cell library and use it without any timing as > > the behavioral model. Synthesis tools do a pretty decent job of doing > > the mapping. > > -- > Jason Thibodeauwww.jayt.orgWhy don't you create a standard cell library yourself? In verilog it should be pretty straightforward.
Reply by ●March 23, 20102010-03-23
On 03/23/2010 09:47 AM, jkljljklk wrote:> On Mar 23, 8:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > wrote: >> I'm sorry, Kal and Ed, I should have been more specific. >> >> I know what the gates are, but they are not defined in the code >> anywhere. I am figuring I need to include a library where they will be >> defined, but I don't know which I should be using, or if any are even >> available in the Xilinx flow. >> >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, >> and when it is synthesized, I have 614 errors since the gates are not >> defined. >> >> I was hoping it would be something as simple as including a library. >> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: >> >> >> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan >>> <ed.mcgetti...@xilinx.com> wrote: >> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >>>> wrote: >>>>> I'm having a terrible time finding a solution to a library problem. >> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>>>> standard cells such as: >> >>>>> AOI21X1 >>>>> AND3X1 >>>>> AND2X1 >>>>> NAND2X1 >> >>>>> etc. >> >>>>> Does anyone have a suggestion? Am I overlooking something simple? >> >>>>> Thanks in advance. >>>>> -- >>>>> Jason Thibodeau >> >>>> The standard cell library should document the function of each these >>>> cells. Likely guesses are. >> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >>>> AND3X1 - 3-Input AND >>>> AND2X1 - 2-Input AND >>>> NAND2X1 - 2-Input NAND >> >>>> etc... = etc... :-) >> >>>> Ed McGettigan >> >>> If we had more info, we can make better guesses. The ports are >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which >>> is OR-inverted with the third ie y = !((a0&a1) | b0). >>> One more thing which is again very helpful is to get the simulation >>> model of the standard cell library and use it without any timing as >>> the behavioral model. Synthesis tools do a pretty decent job of doing >>> the mapping. >> >> -- >> Jason Thibodeauwww.jayt.org > > Why don't you create a standard cell library yourself? In verilog it > should be pretty straightforward.That's what I will do if I can't find a solution, but I'm hoping there is a less time-consuming approach. -- Jason Thibodeau
Reply by ●March 23, 20102010-03-23
On Mar 23, 5:17=A0am, Jason Thibodeau <jason.p.thibod...@gmail.com> wrote:> I'm sorry, Kal and Ed, I should have been more specific. > > I know what the gates are, but they are not defined in the code > anywhere. I am figuring I need to include a library where they will be > defined, but I don't know which I should be using, or if any are even > available in the Xilinx flow. > > I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > and when it is synthesized, I have 614 errors since the gates are not > defined. > > I was hoping it would be something as simple as including a library. > > On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > > > > On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > <ed.mcgetti...@xilinx.com> =A0wrote: > > >> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > >> wrote: > >>> I'm having a terrible time finding a solution to a library problem. > > >>> I am implementing some IWLS benchmarks on a Spartan3e, and I need som=e> >>> standard cells such as: > > >>> AOI21X1 > >>> AND3X1 > >>> AND2X1 > >>> NAND2X1 > > >>> etc. > > >>> Does anyone have a suggestion? Am I overlooking something simple? > > >>> Thanks in advance. > >>> -- > >>> Jason Thibodeau > > >> The standard cell library should document the function of each these > >> cells. =A0Likely guesses are. > > >> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > >> AND3X1 - 3-Input AND > >> AND2X1 - 2-Input AND > >> NAND2X1 - 2-Input NAND > > >> etc... =3D etc... :-) > > >> Ed McGettigan > > > If we had more info, we can make better guesses. The ports are > > extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which > > is OR-inverted =A0with the third ie y =3D !((a0&a1) | b0). > > One more thing which is again very helpful is to get the simulation > > model of the standard cell library and use it without any timing as > > the behavioral model. Synthesis tools do a pretty decent job of doing > > the mapping. > > -- > Jason Thibodeauwww.jayt.org- Hide quoted text - > > - Show quoted text -It should be as simple as "including a library", but this won't come from Xilinx. You need to get it from the creator of the standard cell library that was used to insert these primitives into the HDL code that you are using. This must exist somewhere or simulation would not be possible. When you work this out and run through synthesis the performance of the design will likely be much better with a flatten design so that the basic primitives can be optimized correctly. Ed McGettigan -- Xilinx Inc.
Reply by ●March 23, 20102010-03-23
On 03/23/2010 12:06 PM, Ed McGettigan wrote:> On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > wrote: >> I'm sorry, Kal and Ed, I should have been more specific. >> >> I know what the gates are, but they are not defined in the code >> anywhere. I am figuring I need to include a library where they will be >> defined, but I don't know which I should be using, or if any are even >> available in the Xilinx flow. >> >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, >> and when it is synthesized, I have 614 errors since the gates are not >> defined. >> >> I was hoping it would be something as simple as including a library. >> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: >> >> >> >> >> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan >>> <ed.mcgetti...@xilinx.com> wrote: >> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> >>>> wrote: >>>>> I'm having a terrible time finding a solution to a library problem. >> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I need some >>>>> standard cells such as: >> >>>>> AOI21X1 >>>>> AND3X1 >>>>> AND2X1 >>>>> NAND2X1 >> >>>>> etc. >> >>>>> Does anyone have a suggestion? Am I overlooking something simple? >> >>>>> Thanks in advance. >>>>> -- >>>>> Jason Thibodeau >> >>>> The standard cell library should document the function of each these >>>> cells. Likely guesses are. >> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? >>>> AND3X1 - 3-Input AND >>>> AND2X1 - 2-Input AND >>>> NAND2X1 - 2-Input NAND >> >>>> etc... = etc... :-) >> >>>> Ed McGettigan >> >>> If we had more info, we can make better guesses. The ports are >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs which >>> is OR-inverted with the third ie y = !((a0&a1) | b0). >>> One more thing which is again very helpful is to get the simulation >>> model of the standard cell library and use it without any timing as >>> the behavioral model. Synthesis tools do a pretty decent job of doing >>> the mapping. >> >> -- >> Jason Thibodeauwww.jayt.org- Hide quoted text - >> >> - Show quoted text - > > It should be as simple as "including a library", but this won't come > from Xilinx. You need to get it from the creator of the standard cell > library that was used to insert these primitives into the HDL code > that you are using. This must exist somewhere or simulation would not > be possible. > > When you work this out and run through synthesis the performance of > the design will likely be much better with a flatten design so that > the basic primitives can be optimized correctly. > > Ed McGettigan > -- > Xilinx Inc.This is the direction in which I just headed. I added the GSCLib_3.0.vhd available from the IWLS benchmark tar file. When I add this to the project, I get an error: ERROR:HDLParsers - Cannot rename dependency database for library "ieee", file is "./xst/ieee/hdpdeps.ref", Temporary database file "./xst/xil_7sDTXM" will remain. System error message is: No such file or directory (I had to edit the pathnames in the error message, but the full pathnames are listed in the actuall error message). I was having this same problem yesterday with a different library. When I remove the GSCLib_3.0.vhd file from the project, it reverts to my previous 600+ errors. Any idea what is happening here? -- Jason Thibodeau
Reply by ●March 23, 20102010-03-23
On Tue, Mar 23, 2010 at 12:42 PM, Ed McGettigan
<ed.mcgettigan@xilinx.com> wrote:
On Mar 23, 9:10 am, Jason Thibodeau <jason.p.thibod...@gmail.com>
wrote:
> On 03/23/2010 12:06 PM, Ed McGettigan wrote:
>
>
>
>
>
> > On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com>
> > wrote:
> >> I'm sorry, Kal and Ed, I should have been more specific.
>
> >> I know what the gates are, but they are not defined in the code
> >> anywhere. I am figuring I need to include a library where they
will be
> >> defined, but I don't know which I should be using, or if any
are even
> >> available in the Xilinx flow.
>
> >> I import the (verilog) benchmark, instantiate it in my VHDL
toplevel,
> >> and when it is synthesized, I have 614 errors since the gates
are not
> >> defined.
>
> >> I was hoping it would be something as simple as including a
library.
>
> >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote:
>
> >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan
> >>> <ed.mcgetti...@xilinx.com> wrote:
>
> >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com>
> >>>> wrote:
> >>>>> I'm having a terrible time finding a solution to a library
problem.
>
> >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and
I need some
> >>>>> standard cells such as:
>
> >>>>> AOI21X1
> >>>>> AND3X1
> >>>>> AND2X1
> >>>>> NAND2X1
>
> >>>>> etc.
>
> >>>>> Does anyone have a suggestion? Am I overlooking something
simple?
>
> >>>>> Thanks in advance.
> >>>>> --
> >>>>> Jason Thibodeau
>
> >>>> The standard cell library should document the function of
each these
> >>>> cells. Likely guesses are.
>
> >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs?
> >>>> AND3X1 - 3-Input AND
> >>>> AND2X1 - 2-Input AND
> >>>> NAND2X1 - 2-Input NAND
>
> >>>> etc... = etc... :-)
>
> >>>> Ed McGettigan
>
> >>> If we had more info, we can make better guesses. The ports are
> >>> extremely helpful in fact. Usually AOI21 is AND-OR of two
inputs which
> >>> is OR-inverted with the third ie y = !((a0&a1) | b0).
> >>> One more thing which is again very helpful is to get the
simulation
> >>> model of the standard cell library and use it without any
timing as
> >>> the behavioral model. Synthesis tools do a pretty decent job
of doing
> >>> the mapping.
>
> >> --
> >> Jason Thibodeauwww.jayt.org-Hide quoted text -
>
> >> - Show quoted text -
>
> > It should be as simple as "including a library", but this won't
come
> > from Xilinx. You need to get it from the creator of the
standard cell
> > library that was used to insert these primitives into the HDL code
> > that you are using. This must exist somewhere or simulation
would not
> > be possible.
>
> > When you work this out and run through synthesis the performance of
> > the design will likely be much better with a flatten design so that
> > the basic primitives can be optimized correctly.
>
> > Ed McGettigan
> > --
> > Xilinx Inc.
>
> This is the direction in which I just headed. I added the
GSCLib_3.0.vhd
> available from the IWLS benchmark tar file. When I add this to the
> project, I get an error:
>
> ERROR:HDLParsers - Cannot rename dependency database for library
"ieee",
> file is "./xst/ieee/hdpdeps.ref", Temporary database file
> "./xst/xil_7sDTXM" will remain. System error message is: No
such file
> or directory
>
> (I had to edit the pathnames in the error message, but the full
> pathnames are listed in the actuall error message).
>
> I was having this same problem yesterday with a different
library. When
> I remove the GSCLib_3.0.vhd file from the project, it reverts to my
> previous 600+ errors.
>
> Any idea what is happening here?
>
> --
> Jason Thibodeau- Hide quoted text -
>
> - Show quoted text -
I'm not sure.
Did you compile the GSCLib_3.0 into "library work"? If you tried to
compile it into "library IEEE" that might explain the error message.
It looks like you are using the library that is found here:
http://openedatools.si2.org/cgi-bin/cvsweb.cgi/OAGear/Examples/IWLS/library/GSCLib_3.0.vhd?cvsroot=oagear
If anyone else wants to chime in.
Ed McGettigan
--
Xilinx Inc.
I think Ed mistakenly replied to my email address instead of the group,
so I copied it here.
My response: No I did not compile it into "IEEE", I put it into "work",
and I also tried its own library. Both options gave me the same error.
Reply by ●March 23, 20102010-03-23
On 03/23/2010 01:23 PM, Jason Thibodeau wrote:> > > On Tue, Mar 23, 2010 at 12:42 PM, Ed McGettigan > <ed.mcgettigan@xilinx.com> wrote: > > On Mar 23, 9:10 am, Jason Thibodeau <jason.p.thibod...@gmail.com> > wrote: > > On 03/23/2010 12:06 PM, Ed McGettigan wrote: > > > > > > > > > > > > > On Mar 23, 5:17 am, Jason Thibodeau<jason.p.thibod...@gmail.com> > > > wrote: > > >> I'm sorry, Kal and Ed, I should have been more specific. > > > > >> I know what the gates are, but they are not defined in the code > > >> anywhere. I am figuring I need to include a library where they > will be > > >> defined, but I don't know which I should be using, or if any are even > > >> available in the Xilinx flow. > > > > >> I import the (verilog) benchmark, instantiate it in my VHDL toplevel, > > >> and when it is synthesized, I have 614 errors since the gates are not > > >> defined. > > > > >> I was hoping it would be something as simple as including a library. > > > > >> On 03/23/2010 12:47 AM, Muzaffer Kal wrote: > > > > >>> On Mon, 22 Mar 2010 17:59:29 -0700 (PDT), Ed McGettigan > > >>> <ed.mcgetti...@xilinx.com> wrote: > > > > >>>> On Mar 22, 5:42 pm, Jason Thibodeau<jason.p.thibod...@gmail.com> > > >>>> wrote: > > >>>>> I'm having a terrible time finding a solution to a library > problem. > > > > >>>>> I am implementing some IWLS benchmarks on a Spartan3e, and I > need some > > >>>>> standard cells such as: > > > > >>>>> AOI21X1 > > >>>>> AND3X1 > > >>>>> AND2X1 > > >>>>> NAND2X1 > > > > >>>>> etc. > > > > >>>>> Does anyone have a suggestion? Am I overlooking something simple? > > > > >>>>> Thanks in advance. > > >>>>> -- > > >>>>> Jason Thibodeau > > > > >>>> The standard cell library should document the function of each > these > > >>>> cells. Likely guesses are. > > > > >>>> AOI21X1 - 2-Input AND-OR with Inversion on inputs? > > >>>> AND3X1 - 3-Input AND > > >>>> AND2X1 - 2-Input AND > > >>>> NAND2X1 - 2-Input NAND > > > > >>>> etc... = etc... :-) > > > > >>>> Ed McGettigan > > > > >>> If we had more info, we can make better guesses. The ports are > > >>> extremely helpful in fact. Usually AOI21 is AND-OR of two inputs > which > > >>> is OR-inverted with the third ie y = !((a0&a1) | b0). > > >>> One more thing which is again very helpful is to get the simulation > > >>> model of the standard cell library and use it without any timing as > > >>> the behavioral model. Synthesis tools do a pretty decent job of > doing > > >>> the mapping. > > > > >> -- > > >> Jason Thibodeauwww.jayt.org-Hide quoted text - > > > > >> - Show quoted text - > > > > > It should be as simple as "including a library", but this won't come > > > from Xilinx. You need to get it from the creator of the standard cell > > > library that was used to insert these primitives into the HDL code > > > that you are using. This must exist somewhere or simulation would not > > > be possible. > > > > > When you work this out and run through synthesis the performance of > > > the design will likely be much better with a flatten design so that > > > the basic primitives can be optimized correctly. > > > > > Ed McGettigan > > > -- > > > Xilinx Inc. > > > > This is the direction in which I just headed. I added the GSCLib_3.0.vhd > > available from the IWLS benchmark tar file. When I add this to the > > project, I get an error: > > > > ERROR:HDLParsers - Cannot rename dependency database for library "ieee", > > file is "./xst/ieee/hdpdeps.ref", Temporary database file > > "./xst/xil_7sDTXM" will remain. System error message is: No such file > > or directory > > > > (I had to edit the pathnames in the error message, but the full > > pathnames are listed in the actuall error message). > > > > I was having this same problem yesterday with a different library. When > > I remove the GSCLib_3.0.vhd file from the project, it reverts to my > > previous 600+ errors. > > > > Any idea what is happening here? > > > > -- > > Jason Thibodeau- Hide quoted text - > > > > - Show quoted text - > > I'm not sure. > > Did you compile the GSCLib_3.0 into "library work"? If you tried to > compile it into "library IEEE" that might explain the error message. > > It looks like you are using the library that is found here: > > http://openedatools.si2.org/cgi-bin/cvsweb.cgi/OAGear/Examples/IWLS/library/GSCLib_3.0.vhd?cvsroot=oagear > > > If anyone else wants to chime in. > > Ed McGettigan > -- > Xilinx Inc. > > > I think Ed mistakenly replied to my email address instead of the group, > so I copied it here. > > My response: No I did not compile it into "IEEE", I put it into "work", > and I also tried its own library. Both options gave me the same error.I am writing my own library right now. With any luck I will not encounter the error I have seen previously. Thanks for the suggestions, all. -- Jason Thibodeau
